US 10,789,046 B1 · Low-power fast current-mode meshed multiplication for multiply-accumulate in artificial intelligence

Abstract

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

Claims13

Dependent claims

A meshed multiplier system in an integrated circuit, the system comprising:

a first digital input port for receiving an M-bits wide first digital input word DX;
a second digital input port for receiving an N-bits wide second digital input word DY;
a plurality of N scaled current source banks, each scaled current source bank uniquely corresponding to a bit of DY;
each of the N scaled current source banks comprising a plurality of M scaled current sources, each scaled current source comprised of a corresponding first switch and a corresponding second switch, each current source uniquely corresponding to a bit of the first digital input word DX;
each scaled current source in each scaled current source bank coupled to an input of its corresponding first switch, the first switch responsive to the bit of the first digital input word DX corresponding to the scaled current source;
the first switch comprised of an output coupled to an input of its corresponding second switch, the second switch responsive to the bit of the second digital input word DY corresponding to the scaled current source bank;
the second switch comprised of an output coupled to an output node;
wherein the N scaled current source banks, are at least one of binarily weighted, linearly weighted, and individually weighted;
wherein the plurality of M scaled current sources in each scaled current source bank, are at least one of binarily weighted, linearly weighted, and individually weighted;
and
wherein M is less than 17, and N is less than 17.

8 more elements

A meshed digital-input to analog current-output multiplier system in an integrated circuit, the system comprising:

a digital-input to analog-output multiplier (XDiIo) comprised of a AoXY port, a first digital input port (DX) wherein the DX port is M-bit wide, a second digital input port (DY) wherein the DY port is N-bit wide, and a reference port for receiving a SRu signal;
the XDiIo comprising:
a sequence of M meshed digital-input to analog current-output sub-multipliers (mDiIo), wherein each mDiIo is comprised of a first switch bank (iSW1B), a second switch bank (iSW2B), a current reference signals source bank (SRB), and a first digital 1-bit wide port (BM);
for each mDiIo, each iSW1B switch bank comprised of a sequence of N switches, wherein the N control-ports of the N switches coupled together, and coupled to a 1-bit wide BM port;
for each mDiIo, each iSW2B switch bank comprised of a sequence of N switches, wherein the gate-ports respectively coupled to the DY port;
for each mDiIo, the output ports of the first sequence of N switches of the iSW1B switch bank coupled to the input ports of the second sequence of N switches of the iSW2B switch bank;
for each mDiIo, each SRB signal source bank comprised of a sequence of N current reference signal ports (AR) for receiving sequence of N scaled current reference signals (SR), wherein the sequence of N scaled SR signals is at least one of binarily weighted, linearly weighted, and individually weighted, and wherein each scaled SR signal is proportional to the SRu signal;
for each mDiIo, the sequence of N input ports of the iSW1B switch bank for respectively receiving the sequence of N scaled SR signals of the SRB signal source banks;
for each mDiIo, the sequence of N output ports of the iSW2B switch bank coupled to the AoXY port;
for each mDiIo, the sequence of M 1-bit wide BM ports coupled to the respective M-bit wide DX ports;
wherein for each mDiIo, a sum of the sequence of N of scaled SR signals of the SRB signal source banks is at least one of binarily weighted, linearly weighted, and individually weighted;
and
wherein the XDiIo generates an analog multiplication signal at the AoXY port, that is proportional to the SRu signal, and responsive to the multiplication product of digital words at the DX and the DY ports.

10 more elements

Dependencies are inferred from the claim text.

Low-power fast current-mode meshed multiplication for multiply-accumulate in artificial intelligence

Life of this patent

Low-power fast current-mode meshed multiplication for multiply-accumulate in artificial intelligence

Life of this patent

Abstract

Claims13