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US 10,784,348 B2Granted
Porous semiconductor handle substrate
AssigneeQUALCOMM Incorporated
InventorsStephen Alan Fanelli, Richard Hammond
Life of this patent
Estimating the term…
Abstract
An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.
Claims14
An integrated circuit (IC), comprising:
- an active device layer on a front-side surface of a semiconductor layer on an insulator layer of a semiconductor on insulator (SOI) device substrate;
- a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer;
- and
- a semiconductor handle substrate having a porous semiconductor layer contacting the second surface of the front-side dielectric layer and distal from the SOI device substrate, in which the semiconductor handle substrate is uniformly doped, and the porous semiconductor layer comprises a high porosity portion corresponding to dicing streets on the semiconductor device substrate, a first low porosity portion and a second low porosity portion adjacent to and side-by-side with the high porosity portion, the high porosity portion between the first low porosity portion and the second low porosity portion.
1 more element
An integrated circuit (IC), comprising:
- an active device layer on a front-side surface of a semiconductor layer on an insulator layer of a semiconductor on insulator (SOI) device substrate;
- a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer;
- and
- means for reducing radio frequency (RF) harmonics contacting the second surface of the front-side dielectric layer and distal from the SOI device substrate, and the means for reducing RF harmonics comprising a high porosity portion corresponding to dicing streets on the semiconductor device substrate, a first low porosity portion and a second low porosity portion adjacent to and side-by-side with the high porosity portion, the high porosity portion between the first low porosity portion and the second low porosity portion.
1 more element
Dependencies are inferred from the claim text.