Multiple column per channel CCD sensor architecture for inspection and metrology

A method of inspecting a sample, the method comprising:

• directing and focusing radiation onto the sample while moving the sample relative to a source of said radiation;
• directing received radiation from the sample to an image sensor, the image sensor comprising a multiple-column-per-channel charge-coupled-device (CCD) including an array of pixels arranged in a plurality of rows and a plurality of associated groupsof adjacent columns, each said associated group including at least a first column a second column and a third column;
• driving the image sensor with line clock signals that are synchronized to said moving of the sample relative to the radiation source, the line clock signals causing first and second charges to be respectively transferred along the first, second and third columns from one said row of pixels to an adjacent said row of pixels;
• driving a row of buffer cells of the image sensor with a buffer clock signal, the buffer clock signal causing said first and second charges to be respectively transferred from an edge pixel row of pixels in the first, second and third columns of each associated group of columns to first, second and third buffer cells of the row of buffer cells;
• simultaneously driving with a first transfer clock signal during a first time period a first transfer gate, a third transfer gate and a fifth transfer gate, said first transfer gate being disposed in a first row of said transfer gates and disposed in the first column, the third transfer gate being disposed in a third row of said transfer gates and disposed in the second column, and the fifth transfer gate being disposed in a second row of said transfer gates and disposed in the third column,
• simultaneously driving with a second transfer clock signal during a second time period a seventh transfer gate, an eighth transfer gate and a ninth transfer gate, said seventh transfer gate being disposed in the first row of said transfer gates and disposed in the second column, the eighth transfer gate being disposed in said second row of said transfer gates and disposed in the first column, and the ninth transfer gate being disposed in the third row of said transfer gates and disposed in the third column,
• simultaneously driving with a third transfer clock signal during a third time period a fourth transfer gate, a second transfer gate and a sixth transfer gate, said fourth transfer gate being disposed in the first row of said transfer gates and disposed in the third column, the second transfer gate being disposed in said second row of said transfer gates and disposed in the second column, and the sixth transfer gate being disposed in the third row of said transfer gates and disposed in the first column,
• utilizing an output circuit and an analog-to-digital converter (ADC) circuit to sequentially convert image charges transferred along the first, second and third columns to digital numbers,
• wherein utilizing the ADC circuit includes driving the ADC circuit with a clock frequency greater than at least three times a frequency of the line clock signals.