Device and method for digital to analog conversion
AssigneeRealtek Semiconductor Corp.
InventorChih-Chiang Wang
Life of this patent
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Abstract
A device and a method for digital to analog conversion are provided. The device contains a signal generation circuit and a conversion circuit. The signal generation circuit generates two reset signals which are a first reset signal and a second reset signal. The two reset signals are mutually inverted digital signals and contain the same number of bits. The conversion circuit converts a digital data signal into an analog data signal when a first clock signal is at a first level, and generates the analog data signal at two reset levels respectively according to the two reset signals when the first clock signal is at a second level.
Claims10
A device for digital to analog conversion, comprising:
- a signal generation circuit, configured to generate a first reset signal and a second reset signal, wherein the first reset signal and the second reset signal are mutually inverted and the first reset signal and the second reset signal are digital signals and comprise the same number of bits;
- and
- a first conversion circuit, coupled to the signal generation circuit, and configured to receive a first clock signal and a digital data signal, convert the digital data signal into a first analog data signal when the first clock signal is at a first cycle of a first level, and when the first clock signal is at a second cycle of a second level, generate, according to the first reset signal, the first analog data signal which is at a first reset level after resetting, and generate, according to the second reset signal, the first analog data signal which is at a second reset level after resetting.
A method for digital to analog conversion, comprising:
- generating a first reset signal which is a digital signal by a signal generation circuit;
- generating a second reset signal which is a digital signal by the signal generation circuit, wherein the second reset signal is inverted with respect to the first reset signal, and the second reset signal and the first reset signal comprise the same number of bits;
- receiving a first clock signal, the first reset signal, and the second reset signal by a first conversion circuit, wherein the first clock signal comprises a first level and a second level;
- converting the digital data signal into a first analog data signal by the first conversion circuit when the first clock signal is at a first cycle of the first level;
- generating, by the first conversion circuit according to the first reset signal when the first clock signal is at a second cycle of the second level, the first analog data signal which is at a first reset level after resetting;
- and
- generating, by the first conversion circuit according to the second reset signal when the first clock signal is at the second cycle of the second level, the first analog data signal which is at a second reset level after resetting.
Dependencies are inferred from the claim text.