US 10,778,164 B2Granted

Input receiver circuit and adaptive feedback method

AssigneeWinbond Electronics Corp.

InventorChih-Wei Liang

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Abstract

An adaptive feedback method for use in a memory device is provided. The memory device includes a first input-receiver circuit and a plurality of second input-receiver circuits. The method includes the steps of: providing a clock signal and an inverted clock signal to the first input-receiver circuit; generating an enable control signal by the first input-receiver circuit to control a first feedback path in the first input-receiver circuit; in response to the frequency of the clock signal and the inverted clock signal being higher than or equal to a predetermined frequency, activating the first feedback path in the first input-receiver circuit according to the enable control signal; and in response to the frequency of the clock signal and the inverted clock signal being lower than the predetermined frequency, deactivating the first feedback path in the first input-receiver circuit according to the enable control signal.

Claims11

Dependent claims

An input-receiver circuit, comprising:

a first input receiver, comprising:
a first differential amplifier, configured to receive a clock signal and output an amplified clock signal;
a first buffer circuit, configured to buffer the amplified clock signal and output an output clock signal, wherein there is a first feedback path between the first buffer circuit and the first differential amplifier;
and
a first delay circuit, configured to add a time delay on the amplified clock signal to generate a first delayed signal;
a second input receiver, comprising:
a second differential amplifier, configured to receive an inverted clock signal and output an amplified inverted clock signal;
a second buffer circuit, configured to buffer the amplified inverted clock signal and output an output inverted clock signal, wherein there is a second feedback path between the second buffer circuit and the second differential amplifier;
and
a second delay circuit, configured to add the time delay on the amplified inverted clock signal to generate a second delayed signal;
a control-signal output stage, configured to generate an enable control signal according to the first delayed signal and the second delayed signal, wherein the enable control signal controls activation and deactivation of the first feedback path and the second feedback path.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/153,324Filed 5 Oct 2018
Published: US 2020/0112292 A19 Apr 2020
Granted: 15 Sep 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
H03F 3/4521
Using MOSFET transistors as the active amplifying circuit: complementary long tailed pairs having parallel inputs and being supplied in parallel
G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
G11C 7/225
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock input buffers