Integrated circuit voltage-controlled oscillator with late-stage fabrication tuning

An integrated circuit (IC), the IC comprising:

• a set of lower layers;
• a set of upper layers located above the set of lower layers;
• and
• a tunable circuit having an operating frequency at least partially dependent on a total capacitance of at least one selectable tuning capacitor, wherein the total capacitance of the at least one selectable tuning capacitor is within a range between 8% and 12% of a sum of a capacitance of band capacitors of the tunable circuit, the tunable circuit including:
• a first portion that includes active electronic devices fabricated within the set of lower layers;
• a second portion, fabricated within the set of upper layers, that includes the at least one selectable tuning capacitor having electrically conductive structures separated by dielectric material;
• and
• a set of interconnect structures that is configurable to select a total capacitance of the at least one selectable tuning capacitor by electrically interconnecting the first portion of the tunable circuit to capacitors of the at least one selectable tuning capacitor.

A method, performed by a set of electronic design automation (EDA) tools executed by at least one processor circuit, of modifying an operating frequency of a voltage-controlled oscillator (VCO) circuit within an integrated circuit (IC), the VCO including a first portion containing active electronic devices fabricated within a set of lower layers of the IC, the VCO further including a second portion containing at least one selectable tuning capacitor fabricated within a set of upper layers of the IC, the operating frequency at least partially dependent on a total capacitance of the at least one selectable tuning capacitor, the method comprising:

• extracting, with the set of EDA tools, an initial VCO netlist from an initial VCO layout, the initial VCO layout stored in an IC design file and including the at least one selectable tuning capacitor;
• simulating, with the set of EDA tools, the initial VCO netlist to produce initial simulation results, the initial simulation results being stored in the design file;
• comparing, with the set of EDA tools, the initial simulation results to a set of performance requirements to produce an initial performance difference;
• adjusting, with the set of EDA tools, according to the initial performance difference being outside of a specified range, an amount of selectable tuning capacitance by changing, in the IC design file, data representing a set of interconnect structures configured to electrically connect the first portion of the VCO to the second portion of the VCO, the changing producing, within the IC design file, a modified VCO layout having a modified total capacitance of the at least one selectable tuning capacitor;
• extracting, with the set of EDA tools, a modified VCO netlist from the modified VCO layout;
• simulating, with the set of EDA tools, the modified VCO netlist to produce updated simulation results;
• and
• comparing, with the set of EDA tools, the updated simulation results to the set of performance requirements to produce an updated performance difference.