Method of manufacturing shielded gate trench MOSFET devices

A method for forming shielded gate trench MOSFET devices, including:

• providing a silicon layer having a first type conductivity overlying a semiconductor substrate;
• forming, on a front surface of the silicon layer, an array of a plurality of gate trenches and contact trenches disposed in an alternating fashion in an active region of the front surface, the array of the gate trenches and the contact trenches extending orthogonally from the front surface toward the semiconductor substrate,
• wherein each gate trench defining a first depth and a first width and each contact trench defining a second depth and a second width, and wherein the first depth and the first width are greater than the second depth and the second width, respectively;
• forming in each gate trench a gate trench stack including:
• growing a shield oxide layer including silicon oxide on side walls and a bottom wall of each gate trench;
• forming a first doped poly silicon layer on the shield oxide layer within the gate trench;
• forming a silicon oxide layer on the first doped poly silicon layer;
• forming an undoped poly silicon layer on the silicon oxide layer;
• removing exposed portions of the shield oxide layer from the side walls of the gate trench, which results in exposing surface of the trench side walls above the silicon oxide layer;
• etching the undoped poly silicon layer to expose the silicon oxide layer underneath, wherein etching the undoped poly silicon layer also etches the surface of the side walls, which are exposed, resulting in increasing the width of the gate trench to a third width above the silicon oxide layer with respect to the first width of the gate trench below the silicon oxide layer;
• growing a gate oxide layer on the surface of the trench side walls and all the exposed silicon surfaces;
• and
• forming a second doped poly silicon layer on gate oxide layer and the silicon oxide layer and planarizing it.