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US 10,777,579 B2Granted
Semiconductor integrated circuit device
AssigneeSocionext Inc.
InventorJunji Iwahori
Life of this patent
Estimating the term…
Abstract
In a semiconductor integrated circuit device using three-dimensional transistor devices, a delay cell having a large delay value per unit area is implemented. A first cell, which is a logic cell, includes three-dimensional transistor devices. A second cell, which is a delay cell, includes three-dimensional transistor devices. The length by which a second local interconnect protrudes from a second solid diffusion layer portion in a direction away from a power supply interconnect in the second cell is greater than the length by which a first local interconnect protrudes from a first solid diffusion layer portion in a direction away from the power supply interconnect in the first cell.
Claims17
A semiconductor integrated circuit device, comprising:
- a first standard cell, which is a logic cell, having three-dimensional transistor devices;
- and
- a second standard cell, which is a delay cell, having three-dimensional transistor devices,
- wherein the first standard cell includes:
- a plurality of first solid diffusion layer portions extending in a first direction, the plurality of first solid diffusion layer portions being arranged in a second direction vertical to the first direction, and
- a first local interconnect extending in the second direction and connecting the plurality of first solid diffusion layer portions and a power supply interconnect that extends in the first direction and feeds a predetermined first power supply voltage,
- the second standard cell includes:
- a plurality of second solid diffusion layer portions extending in the first direction, the plurality of second solid diffusion layer portions being arranged in the second direction,
- a second local interconnect extending in the second direction and connecting the plurality of second solid diffusion layer portions and the power supply interconnect, and
- a gate interconnect extending in the second direction to intersect with the plurality of second solid diffusion layer portions as viewed from top, formed to surround the plurality of second solid diffusion layer portions, a signal being applied to the gate interconnect, and
- a length by which the second local interconnect protrudes from the plurality of second solid diffusion layer portions in a direction away from the power supply interconnect in the second standard cell is greater than a length by which the first local interconnect protrudes from the plurality of first solid diffusion layer portions in a direction away from the power supply interconnect in the first standard cell,
- wherein the second standard cell further includes:
- a first interconnect formed above the second local interconnect, and the first interconnect includes:
- a main portion utilized for constructing logic of the second standard cell, and
- a redundant portion, branching from the main portion in a direction different from a direction in which the main portion extends, electrically connected only to the main portion.
12 more elements
A semiconductor integrated circuit device, comprising:
- a first standard cell, which is a logic cell, having three-dimensional transistor devices;
- and
- a second standard cell, which is a delay cell, having three-dimensional transistor devices,
- wherein the first standard cell includes:
- a plurality of first solid diffusion layer portions extending in a first direction, the plurality of first solid diffusion layer portions being arranged in a second direction vertical to the first direction, and
- a first local interconnect extending in the second direction and connecting all the plurality of first solid diffusion layer portions and a power supply interconnect that extends in the first direction and feeds a predetermined first power supply voltage,
- the second standard cell includes:
- a plurality of second solid diffusion layer portions extending in the first direction, the plurality of second solid diffusion layer portions being arranged in the second direction,
- a second local interconnect extending in the second direction and connecting all the plurality of second solid diffusion layer portions and the power supply interconnect, and
- a gate interconnect extending in the second direction to intersect with the plurality of second solid diffusion layer portions as viewed from top, formed to surround the plurality of second solid diffusion layer portions, a signal being applied to the gate interconnect, and
- a length by which the second local interconnect protrudes from one of the plurality of second solid diffusion layer portions in a direction away from the power supply interconnect in the second standard cell, the one of the plurality of second solid diffusion layer portions having most distance from the power supply interconnect among the plurality of second solid diffusion layer portions, is greater than a length by which the first local interconnect protrudes from one of the plurality of first solid diffusion layer portions in a direction away from the power supply interconnect in the first standard cell, the one of the plurality of first solid diffusion layer portions having most distance from the power supply interconnect among the plurality of first solid diffusion layer portions.
8 more elements
Dependencies are inferred from the claim text.