Memory array for processing an N-bit word

A method for processing an N-bit word in a memory array, the memory array comprising:

• a data block comprising N serially connected cells, each cell of the cells comprising a memory element storing a respective bit of the word, a charge adding unit and a switching logic, wherein the last cell of the cells is further configured to receive a sequence of M bits;
• and
• an output block serially connected to the data block, comprising a result accumulation unit;
• the method comprising
• providing a 3-phase clocking scheme having a sequence of M groups of clock cycles associated with the respective sequence of M bits;
• for each group of the M groups, applying the phases during the clock cycles of that group in accordance with the 3-phase scheme such that the voltage across the charge adding unit of the last cell is the analog voltage which corresponds to the N-bit word scaled by the bit associated with said group;
• and
• accumulating the scaled voltage during a clock cycle following said group in response to the application of a phase of the three phases.

A computer program product comprising a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code configured for processing an N-bit word in a memory array, the memory array comprising:

• a data block comprising N serially connected cells, each cell of the cells comprising a memory element storing a respective bit of the word, a charge adding unit and a switching logic, wherein the last cell of the cells is further configured to receive a sequence of M bits;
• and an output block serially connected to the data block, comprising a result accumulation unit;
• the computer-readable program code configured for:
• for each group of the M groups, applying phases during clock cycles of that group in accordance with a 3-phase scheme such that the voltage across the charge adding unit of the last cell is the analog voltage which corresponds to the N-bit word scaled by the bit associated with said group;
• accumulating the scaled voltage during a clock cycle following said group in response to the application of a phase of the three phases.