Method for cycle accurate data transfer in a skewed synchronous clock domain

A method for performing data write and data read operations on a data register in a skewed synchronous clock domain, said method comprising the following steps:

• initializing on reset, Least Significant Bit (LSB) of a write address register to ‘1’, and initializing remaining bits of the write address register to ‘0’, such that the LSB of the write address register holds 1′ and at least a Most Significant Bit (MSB) of the write address register holds ‘0’;
• initializing on the reset, Least Significant Bit (LSB) of a read address register to ‘1’, and initializing remaining bits of the read address register to ‘0’, such that the LSB of the read address register holds ‘1’, and at least a Most Significant Bit (MSB) of the read address register holds ‘0’;
• issuing a source clock after the reset and extracting data stored in a memory location pointed to by a write address register bit storing a value ‘1’, and preparing for extracted data to be pushed into the data register;
• inverting original bits of said write address register and generating inverted bits, and performing a first AND operation between the inverted bits and contents previously stored in the data register, and generating a first bit pattern as a resultant of said first AND operation;
• performing a second AND operation between the original bits of the write address register and the data to be pushed into the data register, and generating a second bit pattern as a resultant of said second AND operation;
• performing a first OR operation on said first bit pattern and second bit pattern, and updating the data register based on resultant of said first OR operation;
• issuing a skewed source synchronous clock after the reset, and performing an AND operation between bits of the read address register and the contents stored in the data register, and generating a third bit pattern;
• performing a second OR operation on said third bit pattern, and reading data stored in the data register, based on resultant of said second OR operation.