# US 10,771,982 B2 · Resource utilization of heterogeneous compute units in electronic design automation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,771,982 B2 - Document ID: US10771982B2 - Status: Granted - Kind: B2 - Application number: 16/169,306 - Filed: 2018-10-24 - Published: 2020-04-30 - Granted: 2020-09-08 - Earliest claimed: 2018-10-24 - Assignees: Mentor Graphics Corporation - Applicants: Mentor Graphics Corporation - Inventors: Patrick D. Gibson; Robert A. Todd - Web page: https://patentgrep.com/patent/US10771982B2 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - H04W 16/10: Dynamic resource partitioning - G06F 9/5061: {Partitioning or combining of resources} - H04L 5/0032: {Distributed allocation, i.e. involving a plurality of allocating devices, each making partial allocation} - H04W 24/02: Arrangements for optimising operational condition - G06F 2111/02: CAD in a network environment, e.g. collaborative CAD or distributed simulation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A system may include a pool of heterogeneous compute units configured to execute an electronic design automation (EDA) application for design or verification of a circuit, wherein the pool of heterogeneous compute units includes compute units with differing computing capabilities. The system may also include a resource utilization engine configured to identify an EDA operation to be performed for the EDA application, select a compute unit among the pool of heterogeneous compute units to execute the EDA operation based on a determined computing capability specific to the selected compute unit, and assign execution of the EDA operation to the selected compute unit. ## Claims ### Claim 1 A method performed by a computing system, the method comprising: identifying a pool of heterogeneous compute units configured to execute an electronic design automation (EDA) application for design or verification of a circuit, wherein the pool of heterogeneous compute units includes a plurality of compute units with differing computing capabilities; identifying an EDA operation to be performed for the EDA application; selecting a compute unit among the pool of heterogeneous compute units to execute the EDA operation based on a determined computing capability specific to the selected compute unit; and assigning an execution of the EDA operation to the selected compute unit, wherein the determined computing capability comprises a performance benchmark for the EDA operation specific to the selected compute unit, and further comprising obtaining, for different EDA operations, performance benchmarks for the plurality of compute units included in the pool of heterogeneous compute units, including by: issuing benchmark operations specific to the different EDA operations to each of the plurality of compute units included in the pool of heterogeneous compute units; and tracking performance of each of the plurality of compute units in executing the issued benchmark operations. ### Claim 2 (depends on 1) The method of claim 1, wherein the determined computing capability further comprises a threshold number of central processing units (CPUs), a threshold processor speed, a threshold memory speed, or a threshold amount of available memory. ### Claim 3 (depends on 1) The method of claim 1, wherein the selecting comprises: identifying a particular computing capability relevant to the EDA operation; and selecting a particular compute unit from among the pool of heterogeneous compute units with a highest measure of the particular computing capability. ### Claim 4 (depends on 1) The method of claim 1, wherein the EDA operation is a design-rule-check (DRC) operation; and wherein the selecting comprises selecting a particular compute unit among the pool of heterogeneous compute units to perform the DRC operation with a highest processor speed, a highest cache memory speed, or a combination of both. ### Claim 5 (depends on 1) The method of claim 1, wherein the EDA operation is a lithography operation; and wherein the selecting comprises selecting a particular compute unit among the pool of heterogeneous compute units to perform the lithography operation with a highest main memory speed. ### Claim 6 (depends on 1) The method of claim 1, comprising obtaining the performance benchmarks for the plurality of compute units and selecting the computing unit among the pool of heterogeneous compute units to execute the EDA operation without determining specific resource configurations of the plurality of computing units. ### Claim 7 A system comprising: a pool of heterogeneous compute units configured to execute an electronic design automation (EDA) application for design or verification of a circuit, wherein the pool of heterogeneous compute units includes a plurality of compute units with differing computing capabilities; and a resource utilization engine configured to: identify an EDA operation to be performed for the EDA application; select a compute unit among the pool of heterogeneous compute units to execute the EDA operation based on a determined computing capability specific to the selected compute unit; and assign an execution of the EDA operation to the selected compute unit, wherein the determined computing capability comprises a performance benchmark for the EDA operation specific to the selected compute unit, and wherein the resource utilization engine is further configured to obtain, for different EDA operations, performance benchmarks for the plurality of compute units included in the pool of heterogeneous compute units, including by: issuing benchmark operations specific to the different EDA operations to each of the plurality of compute units included in the pool of heterogeneous compute units; and tracking performance of each of the plurality of compute units in executing the issued benchmark operations. ### Claim 8 (depends on 7) The system of claim 7, wherein the determined computing capability further comprises a threshold number of central processing units (CPUs), a threshold processor speed, a threshold memory speed, or a threshold amount of available memory. ### Claim 9 (depends on 7) The system of claim 7, wherein the resource utilization engine is configured to select the compute unit by: identifying a particular computing capability relevant to the EDA operation; and selecting a particular compute unit from among the pool of heterogeneous compute units with a highest measure of the particular computing capability. ### Claim 10 (depends on 7) The system of claim 7, wherein: the EDA operation is a design-rule-check (DRC) operation; and the resource utilization engine is configured to select a particular compute unit among the pool of heterogeneous compute units to perform the DRC operation with a highest processor speed, a highest cache memory speed, or a combination of both. ### Claim 11 (depends on 7) The system of claim 7, wherein: the EDA operation is a lithography operation; and the resource utilization engine is configured to select a particular compute unit among the pool of heterogeneous compute units to perform the lithography operation with a highest main memory speed. ### Claim 12 (depends on 7) The system of claim 7, wherein the resource utilization engine is configured to obtain the performance benchmarks for the plurality of compute units and select the computing unit among the pool of heterogeneous compute units to execute the EDA operation without determining specific resource configurations of the plurality of computing units. ### Claim 13 (depends on 7) The system of claim 7, wherein the performance benchmarks comprise execution latencies for executions of the EDA operation by the plurality of computing units. ### Claim 14 A non-transitory machine-readable medium comprising instructions that, when executed by a processor, cause a system to: identify a pool of heterogeneous compute units configured to execute an electronic design automation (EDA) application for design or verification of a circuit, wherein the pool of heterogeneous compute units includes a plurality of compute units with differing computing capabilities; identify an EDA operation to be performed for the EDA application; select a compute unit among the pool of heterogeneous compute units to execute the EDA operation based on a determined computing capability specific to the selected compute unit; and assign an execution of the EDA operation to the selected compute unit, wherein the determined computing capability comprises a performance benchmark for the EDA operation specific to the selected compute unit, and wherein the instructions, when executed by the processor, further cause the system to obtain, for different EDA operations, performance benchmarks for the plurality of compute units included in the pool of heterogeneous compute units, including by: issuing benchmark operations specific to the different EDA operations to each of the plurality of compute units included in the pool of heterogeneous compute units; and tracking performance of each of the plurality of compute units in executing the issued benchmark operations. ### Claim 15 (depends on 14) The non-transitory machine-readable medium of claim 14, wherein the determined computing capability further comprises a threshold number of central processing units (CPUs), a threshold processor speed, a threshold memory speed, or a threshold amount of available memory. ### Claim 16 (depends on 14) The non-transitory machine-readable medium of claim 14, wherein the instructions to select a compute unit among the pool of heterogeneous compute units comprise instructions that, when executed, cause the system to: identify a particular computing capability relevant to the EDA operation; and select a particular compute unit from among the pool of heterogeneous compute units with a highest measure of the particular computing capability. ### Claim 17 (depends on 14) The non-transitory machine-readable medium of claim 14, wherein: the EDA operation is a design-rule-check (DRC) operation; and the instructions to select the compute unit comprise instructions that, when executed, cause the system to select a particular compute unit among the pool of heterogeneous compute units to perform the DRC operation with a highest processor speed, a highest cache memory speed, or a combination of both. ### Claim 18 (depends on 14) The non-transitory machine-readable medium of claim 14, wherein: the EDA operation is a lithography operation; and the instructions to select the compute unit comprise instructions that, when executed, cause the system to select a particular compute unit among the pool of heterogeneous compute units to perform the lithography operation with a highest main memory speed. ### Claim 19 (depends on 14) The non-transitory machine-readable medium of claim 14, wherein the instructions, when executed by the processor, cause the system to obtain the performance benchmarks for the plurality of compute units and select the computing unit among the pool of heterogeneous compute units to execute the EDA operation without determining specific resource configurations of the plurality of computing units. ### Claim 20 (depends on 14) The non-transitory machine-readable medium of claim 14, wherein the performance benchmarks comprise execution latencies for executions of the EDA operation by the plurality of computing units.