# US 10,771,233 B1 · Clock data recovery circuit

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- Number: US 10,771,233 B1
- Document ID: US10771233B1
- Status: Granted
- Kind: B1
- Application number: 16/793,267
- Filed: 2020-02-18
- Published: 2020-08-20
- Granted: 2020-09-08
- Earliest claimed: 2019-02-19
- Assignees: Realtek Semiconductor Corp.
- Applicants: Realtek Semiconductor Corp.
- Inventors: Yao-Chia Liu; Chi-Wei Yen; Wei-Zen Chen
- Web page: https://patentgrep.com/patent/US10771233B1

## CPC

- H04L 7/04: Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)}
- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- H03L 7/081: provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/099: concerning mainly the controlled oscillator of the loop
- H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence)
- H04L 7/0025: {interpolation of clock signal}
- H03L 2207/06: Phase locked loops with a controlled oscillator having at least two frequency control terminals
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A clock data recovery circuit includes: a first detecting circuit for detecting phases of an incoming data signal and a sampling clock signal to generate a first detection signal; a loop filter for generating a control signal according to the first detection signal; a second detecting circuit for detecting phases of a reference signal and a feedback signal to generate a second detection signal; a control voltage generating circuit for generating a control voltage based on the second detection signal; a voltage-controlled oscillator for generating the sampling clock signal according to the control voltage; a phase adjustment circuit for adjusting the phase of the sampling clock signal according to the control signal to generate the phase-adjusted signal; and a frequency divider circuit for conducting a frequency division operation on the phase-adjusted signal to generate the feedback signal.

## Claims

### Claim 1

A clock data recovery circuit (100), comprising:
a first detecting circuit (110), arranged to operably detect phases of a data signal (DA_IN) and a sampling clock signal (SCLK) to generate a corresponding first detection signal (DEC1);
a first loop filter (120), coupled with the first detecting circuit (110), and arranged to operably process the first detection signal (DEC1) to generate a control signal (CTL);
a second detecting circuit (130), arranged to operably detect phases of a reference signal (REF) and a feedback signal (FB) to generate a corresponding second detection signal (DEC2);
a control voltage generating circuit (140), coupled with the second detecting circuit (130), and arranged to operably generate a corresponding control voltage (VC) according to the second detection signal (DEC2);
a voltage-controlled oscillator (150), coupled with the control voltage generating circuit (140), and arranged to operably generate the sampling clock signal (SCLK) according to the control voltage (VC);
a phase adjustment circuit (160), coupled with the first loop filter (120) and the voltage-controlled oscillator (150), and arranged to operably adjust a phase of the sampling clock signal (SCLK) according to the control signal (CTL), so as to generate a phase-adjusted signal (ACLK); and
a frequency divider circuit (170), coupled with the second detecting circuit (130) and the phase adjustment circuit (160), and arranged to operably conduct a frequency division operation on the phase-adjusted signal (ACLK) to generate the feedback signal (FB).

### Claim 2 (depends on 1)

The clock data recovery circuit (100) of claim 1, further comprising:
an adjustment circuit (180), coupled with the first detecting circuit (110) and the voltage-controlled oscillator (150), and arranged to operably control the voltage-controlled oscillator (150) according to the first detection signal (DEC1) to change the phase of the sampling clock signal (SCLK).

### Claim 3 (depends on 2)

The clock data recovery circuit (100) of claim 2, wherein the adjustment circuit (180) is arranged to operably adjust a current passing through the voltage-controlled oscillator (150) according to the first detection signal (DEC1) to thereby change the phase of the sampling clock signal (SCLK).

### Claim 4 (depends on 2)

The clock data recovery circuit (100) of claim 2, wherein the control voltage generating circuit (140) comprises:
a charge pump (242), coupled with the second detecting circuit (130), and arranged to operably generate a corresponding output voltage according to the second detection signal (DEC2); and
a second loop filter (244), coupled with the charge pump (242) and the voltage-controlled oscillator (150), and arranged to operably compensate and filter the output voltage, so as to generate the control voltage (VC).

### Claim 5 (depends on 2)

The clock data recovery circuit (100) of claim 2, wherein the adjustment circuit (180) comprises:
a current source circuit (282), arranged to operably increase the current passing through the voltage-controlled oscillator (150) according to the first detection signal (DEC1).

### Claim 6 (depends on 2)

The clock data recovery circuit (100) of claim 2, wherein the adjustment circuit (180) comprises:
a current sink circuit (284), arranged to operably decrease the current passing through the voltage-controlled oscillator (150) according to the first detection signal (DEC1).

### Claim 7 (depends on 2)

The clock data recovery circuit (100) of claim 2, wherein the adjustment circuit (180) comprises:
a current source circuit (282), arranged to operably increase the current passing through the voltage-controlled oscillator (150) according to the first detection signal (DEC1); and
a current sink circuit (284), arranged to operably decrease the current passing through the voltage-controlled oscillator (150) according to the first detection signal (DEC1).

### Claim 8 (depends on 2)

The clock data recovery circuit (100) of claim 2, wherein when the clock data recovery circuit (100) operates, the first detecting circuit (110), the adjustment circuit (180), and the voltage-controlled oscillator (150) form a first loop, while the second detecting circuit (130), the control voltage generating circuit (140), the voltage-controlled oscillator (150), the phase adjustment circuit (160), and the frequency divider circuit (170) form a second loop, and the first loop and the second loop both share the sampling clock signal (SCLK) generated by the voltage-controlled oscillator (150) at the same time.