# US 10,771,231 B2 · Signaling system with adaptive timing calibration

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- Number: US 10,771,231 B2
- Document ID: US10771231B2
- Status: Granted
- Kind: B2
- Application number: 16/584,830
- Filed: 2019-09-26
- Published: 2020-04-02
- Granted: 2020-09-08
- Earliest claimed: 2006-03-16
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Bret G. Stott; Craig E. Hampel; Frederick A. Ware
- Web page: https://patentgrep.com/patent/US10771231B2

## CPC

- H04L 7/0337: {Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals}
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/1093: {Input synchronization}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- H03L 7/0812: {and where no voltage or current controlled oscillator is used}
- H03L 7/0814: {the phase shifting device being digitally controlled}
- H04L 1/203: {Details of error rate determination, e.g. BER, FER or WER}
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- H04L 7/0037: {Delay of clock signal}
- H04L 7/0041: {Delay of data signal}
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 2207/2254: Calibration
- H04L 7/0004: {Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

## Claims

### Claim 1

An integrated circuit (IC) memory controller, comprising:
a timing signal pin to receive a timing signal;
a data pin to receive data during live data transfer operations and having sampling circuitry;
a timing controller coupled to the timing signal pin and the data pin, the timing controller operative during an initialization mode to determine whether devices generating the data support an adaptive calibration mode associated with the live data transfer operations, the initialization mode occurring outside of the live data transfer operations, the timing controller operative during the adaptive calibration mode to detect a phase difference between a phase of the timing signal and a phase of the data, and to adjust the phase of the data to a calibrated phase based on the phase difference; and
wherein the sampling circuitry samples the data based on the calibrated phase.

### Claim 2 (depends on 1)

The integrated circuit (IC) memory controller of claim 1 wherein:
the data pin includes a first adjustable delay circuit responsive to the timing controller to delay the data by a delay value based on the phase difference.

### Claim 3 (depends on 1)

The integrated circuit (IC) memory controller of claim 1 wherein the detected phase difference is based on a differential phase error signal corresponding to a phase difference between a phase of the timing signal and a phase of the data.

### Claim 4 (depends on 3)

The integrated circuit (IC) memory controller of claim 3 wherein the differential phase error signal comprises a difference between a positive edge bit error rate (BER) that indicates a rate of errors in sampling early and a negative edge BER that indicates a rate of errors in sampling late.

### Claim 5 (depends on 1)

The integrated circuit (IC) memory controller of claim 1 wherein the timing signal is a strobe signal.

### Claim 6 (depends on 1)

The integrated circuit (IC) memory controller of claim 1 wherein:
the timing controller is operative to adaptively adjust the phase of the timing signal based on a most recently generated calibrated phase.

### Claim 7 (depends on 1)

The integrated circuit (IC) memory controller of claim 1 wherein the timing controller includes a multiplexer having an input corresponding to the phase of the data, the multiplexer having an output to provide the calibrated phase in a sequenced manner with other calibrated phases associated with other data.

### Claim 8

A method of operation in an integrated circuit (IC) memory controller, comprising:
receiving a timing signal, the timing signal exhibiting a first phase;
receiving data during live data transfer operations, the data exhibiting a second phase;
during an initialization mode
determining whether devices generating the data support an adaptive calibration mode associated with the live data transfer operations, the initialization mode occurring outside of the live data transfer operations;
during the adaptive calibration mode
detecting a phase difference between the first phase of the timing signal and the second phase of the data,
adjusting the second phase of the data to a calibrated phase based on the phase difference, and
sampling the data based on the calibrated phase.

### Claim 9 (depends on 8)

The method of claim 8, wherein the adjusting the second phase includes delaying the data with an adjustable delay circuit by a delay value based on the phase difference.

### Claim 10 (depends on 8)

The method of claim 8 wherein detecting the phase difference comprises evaluating a differential phase error signal representing the phase difference.

### Claim 11 (depends on 10)

The method of claim 10, wherein the differential phase error signal comprises a difference between a positive edge bit error rate (BER) that indicates a rate of errors in sampling early and a negative edge BER that indicates a rate of errors in sampling late.

### Claim 12 (depends on 8)

The method according to claim 8 wherein the timing signal comprises a strobe signal.

### Claim 13 (depends on 8)

The method according to claim 8, further comprising:
adaptively adjusting the first phase of the timing signal based on a most recently generated calibrated phase.

### Claim 14 (depends on 8)

The method according to claim 8, further comprising time-multiplexing the second phase and other data phases to generate a sequence of calibrated phases.

### Claim 15

A method of operation in an integrated circuit (IC) memory controller, comprising:
during an initialization mode of operation,
determining whether devices generating data support an adaptive calibration mode associated with live data transfer operations, the initialization mode occurring outside of the live data transfer operations;
during the adaptive calibration mode of operation that occurs during the live data transfer operations,
calibrating a data path delay value for delaying data associated with a data path, the calibrating for the data path done in a sequential manner with respect to other data paths, the data path delay value being calibrated by
receiving data from a given data path, the data exhibiting a data signal phase,
detecting a phase difference between a timing signal phase and the data signal phase, and
determining an updated delay value based on the detected phase difference; and
sampling data from the data path based on the determined updated delay value for the data path.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
during the initialization mode of operation prior to the adaptive calibration mode of operation, calibrating an initial timing path delay value and an initial data path delay value.

### Claim 17 (depends on 15)

The method of claim 15, wherein detecting the phase difference comprises evaluating a differential phase error signal representing the phase difference.

### Claim 18 (depends on 17)

The method of claim 17, wherein the differential phase error signal comprises a difference between a positive edge bit error rate (BER) that indicates a rate of errors in sampling early and a negative edge BER that indicates a rate of errors in sampling late.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
calibrating a timing path delay value based on a phase difference between the timing signal phase and data associated with the data path, the timing path delay value to adjust the timing signal phase to a calibrated timing signal phase.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
after determining an updated delay value based on the detected phase difference, applying the updated delay value to delay the data received via the data path.