# US 10,771,093 B2 · Apparatus to improve flexibility of data transmission > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,771,093 B2 - Document ID: US10771093B2 - Status: Granted - Kind: B2 - Application number: 16/250,097 - Filed: 2019-01-17 - Published: 2019-05-16 - Granted: 2020-09-08 - Earliest claimed: 2014-10-17 - Assignees: Sony Corporation - Applicants: Sony Corporation - Inventors: Ryota Kimura; Yifu Tang - Web page: https://patentgrep.com/patent/US10771093B2 ## CPC - H03M 13/2792: {Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing} - H03M 13/2778: {Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices} - H03M 13/2789: {Interleaver providing variable interleaving, e.g. variable block sizes} - H04L 1/00: Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} - H04L 1/0058: {Block-coded modulation} - H04L 1/0071: {Use of interleaving (interleaving per se H03M13/27)} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract There is provided an apparatus including an acquisition unit configured to acquire an information block generated from transmission data for a user and subjected to error correction coding and an interleaving unit configured to interleave a bit sequence of the information block using an interleaver unique to the user. The interleaving unit interleaves the bit sequence by interleaving each of two or more partial sequences obtained from the bit sequence. ## Claims ### Claim 1 An apparatus, comprising: circuitry configured to: acquire an information block from transmission data, wherein the information block is subjected to an error correction coding operation; and interleave a bit sequence of the information block, wherein the interleave of the bit sequence is based on interleave of each of a plurality of partial sequences obtained from the bit sequence, and a length of the bit sequence is a power of a number other than two. ### Claim 2 (depends on 1) The apparatus according to claim 1, wherein a length of each of the plurality of partial sequences is a power of two. ### Claim 3 (depends on 1) The apparatus according to claim 1, wherein the information block is one of a codeword or a code block. ### Claim 4 (depends on 1) The apparatus according to claim 1, wherein: the circuitry is further configured to interleave each of the plurality of partial sequences by a corresponding interleaver, and a length of the corresponding interleaver is equal to a length of one of the plurality of partial sequences, and the corresponding interleaver is unique to a user. ### Claim 5 (depends on 1) The apparatus according to claim 1, wherein: each of the plurality of partial sequences is included in the bit sequence, and a first partial sequence of the plurality of partial sequences non-overlaps with a second partial sequence of the plurality of partial sequences. ### Claim 6 (depends on 5) The apparatus according to claim 5, wherein a total sum of lengths of the plurality of partial sequences is equal to the length of the bit sequence. ### Claim 7 (depends on 5) The apparatus according to claim 5, wherein the plurality of partial sequences have different lengths. ### Claim 8 (depends on 5) The apparatus according to claim 5, wherein the circuitry is further configured to interleave the plurality of partial sequences in parallel. ### Claim 9 (depends on 5) The apparatus according to claim 5, wherein: the circuitry is further configured to interleave the bit sequence based on a concatenated interleaver, wherein the concatenated interleaver includes a first interleaver corresponding to each of the plurality of partial sequences, and a length of the concatenated interleaver is equal to the length of the bit sequence, a length of the first interleaver corresponding to each of the plurality of partial sequences is equal to a length of one of the plurality of partial sequences, and the first interleaver is unique to a user. ### Claim 10 (depends on 1) The apparatus according to claim 1, wherein a first partial sequence of the plurality of partial sequences further includes a part of the bit sequence. ### Claim 11 (depends on 1) The apparatus according to claim 1, wherein a total sum of lengths of the partial sequences is greater than the length of the bit sequence. ### Claim 12 (depends on 1) The apparatus according to claim 1, wherein the plurality of partial sequences have a same length. ### Claim 13 (depends on 1) The apparatus according to claim 1, wherein a length of each of the plurality of partial sequences is based on the length of the bit sequence, and the length of each of the plurality of partial sequences is among a plurality of lengths. ### Claim 14 (depends on 1) The apparatus according to claim 1, wherein a length of each of the plurality of partial sequences is a same length. ### Claim 15 An apparatus, comprising: circuitry configured to: acquire a bit sequence, wherein a length of the bit sequence is a power of a number other than two; and generate an information block by de-interleave of the acquired bit sequence based on a de-interleaver, wherein the de-interleaver corresponds to an interleaver unique to a user, the de-interleave of the acquired bit sequence is by de-interleave of each of at least two partial sequences obtained from the acquired bit sequence, and the information block is non-decoded for error correction. ### Claim 16 An apparatus, comprising: circuitry configured to: acquire an information block from transmission data, wherein the information block is subjected to an error correction coding operation; and interleave a bit sequence based on one of a first interleaver or a second interleaver obtained from the first interleaver, wherein the second interleaver is longer than the bit sequence of the information block, a plurality of partial sequences are obtained from the bit sequence, and a length of the bit sequence is a power of a number other than two.