# US 10,771,091 B2 · Flash memory apparatus and storage management method for flash memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,771,091 B2 - Document ID: US10771091B2 - Status: Granted - Kind: B2 - Application number: 16/251,033 - Filed: 2019-01-17 - Published: 2019-06-06 - Granted: 2020-09-08 - Earliest claimed: 2016-04-27 - Applicants: Silicon Motion Inc. - Inventors: Tsung-Chieh Yang; Hong-Jung Hsu - Web page: https://patentgrep.com/patent/US10771091B2 ## CPC - H03M 13/098: {using single parity bit} - G06F 11/1072: {in multilevel memories} - G06F 11/108: {Parity data distribution in semiconductor storages, e.g. in SSD} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/10: Programming or data input circuits - H03M 13/1515: {Reed-Solomon codes} - H03M 13/611: {Specific encoding aspects, e.g. encoding by means of decoding} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks. ## Claims ### Claim 1 A flash memory apparatus, comprising: a flash memory module comprising a plurality of first blocks and at least one second block; and a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) RS (Reed-Solomon) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of first blocks; wherein when completing program of the plurality of first blocks, controlling the flash memory module to perform an internal copy operation to program the at least one second block of the flash memory module according to the plurality of first blocks of the flash memory module; a cell of one first block is used for storing a data amount smaller than a data amount stored by a cell of one second block. ### Claim 2 (depends on 1) The flash memory apparatus of claim 1, wherein a cell of the plurality of first blocks is arranged for storing data of two bits, and a cell of the second block is arranged for storing data of 2N bits, N being an integer equal to 2 or greater than 2. ### Claim 3 (depends on 2) The flash memory apparatus of claim 2, wherein N is equal to 3, and the at least one second block is a triple-level-cell block, and the flash memory controller is arranged for classifying the data to be programmed into three groups of data to respectively program the three groups of data into three single-level-cell blocks. ### Claim 4 (depends on 2) The flash memory apparatus of claim 2, wherein the plurality of first blocks are a plurality of single-level-cell (SLC) blocks, when programming a group of data to a single-level-cell block, the flash memory controller is arranged for sequentially organizing and classifying every (M) word lines of all word lines of the single-level-cell block into a group of word lines to generate a plurality of odd groups of word lines and a plurality of even groups of word lines, for respectively executing different Reed-Solomon encoding operations upon the plurality of odd groups of word lines and the plurality of even groups of word lines to generate a first parity check code of the odd groups of word lines and a second parity check code of the even groups of word lines, for programming and storing the first parity check code at last data pages of a last word line of a last group among the plurality of odd groups of word lines, and for programming and storing the second parity check code at last data pages of a last word line of a last group among the plurality of even groups of word lines. ### Claim 5 (depends on 1) The flash memory apparatus of claim 1, wherein when performing memory garbage collection, the flash memory controller is arranged for externally reading out and retrieving data from the plurality of first blocks or from the at least one second block for re-encoding and re-programming the read out and retrieved data. ### Claim 6 (depends on 1) The flash memory apparatus of claim 1, wherein when programming data into a first block and shutdown occurring, the flash memory controller is arranged to read back data from the first block and re-encode and program the read back data into another first. ### Claim 7 (depends on 1) The flash memory apparatus of claim 1, wherein when programming data into the at least one second block and shutdown occurring, the flash memory module is arranged to discard data stored by the at least one second block and perform the internal copy operation to copy and program data from the plurality of first blocks into the at least one second block. ### Claim 8 (depends on 1) The flash memory apparatus of claim 1, wherein when programming data into the plurality of first blocks, the flash memory controller is arranged to program data into the plurality of first blocks according to a randomizer seed rule of the at least one second block. ### Claim 9 (depends on 1) The flash memory apparatus of claim 1, wherein the flash memory module is controlled to perform the internal copy operation by sequentially reading the groups of data and the corresponding parity check code from the plurality of first blocks and then writing the groups of data and the corresponding parity check code, read from the plurality of first blocks, to the at least one second block according to an order of storing the groups of data and the corresponding parity check code in the plurality of first blocks. ### Claim 10 A flash memory storage management method used in a flash memory module having a plurality of first blocks and at least one second block, comprising: classifying data to be programmed into a plurality of groups of data; respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) RS (Reed-Solomon) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of first blocks; and controlling the flash memory module to perform an internal copy operation to program the at least one second block of the flash memory module according to the plurality of first blocks of the flash memory module; a cell of one first block is used for storing a data amount smaller than a data amount stored by a cell of one second block. ### Claim 11 (depends on 10) The method of claim 10, wherein a cell of the plurality of first blocks is arranged for storing data of two bits, and a cell of the second block is arranged for storing data of 2N bits, N being an integer equal to 2 or greater than 2. ### Claim 12 (depends on 11) The method of claim 11, wherein N is equal to 3, and the at least one second block is a triple-level-cell block, and the classifying step comprises: classifying the data to be programmed into three groups of data to respectively program the three groups of data into three first blocks. ### Claim 13 (depends on 11) The method of claim 11, wherein the plurality of first blocks are a plurality of single-level-cell (SLC) blocks, and the executing step comprise: when programming a group of data to a single-level-cell block, sequentially organizing and classifying every (M) word lines of all word lines of the single-level-cell block into a group of word lines to generate a plurality of odd groups of word lines and a plurality of even groups of word lines; respectively executing different Reed-Solomon encoding operations upon the plurality of odd groups of word lines and the plurality of even groups of word lines to generate a first parity check code of the odd groups of word lines and a second parity check code of the even groups of word lines, programming and storing the first parity check code at last data pages of a last word line of a last group among the plurality of odd groups of word lines; and programming and storing the second parity check code at last data pages of a last word line of a last group among the plurality of even groups of word lines. ### Claim 14 (depends on 10) The method of claim 10, further comprising: when performing memory garbage collection, reading out and retrieving data from the plurality of first blocks or from the at least one second block for re-encoding and re-programming the read out and retrieved data. ### Claim 15 (depends on 10) The method of claim 10, further comprising: when programming data into a first block and shutdown occurring, reading back data from the first block and re-encode and program the read back data into another first block. ### Claim 16 (depends on 10) The method of claim 10, further comprising: when programming data into the at least one second cell block and shutdown occurring, discarding data stored by the at least one second block and performing the internal copy operation to copy and program data from the plurality of first blocks into the at least one second block. ### Claim 17 (depends on 10) The method of claim 10, further comprising: when programming data into the plurality of first blocks, programming data into the plurality of first blocks according to a randomizer seed rule of the at least one second block. ### Claim 18 (depends on 10) The method of claim 10, wherein the step of controlling the flash memory module to perform the internal copy operation comprises: controlling the flash memory module to: sequentially reading the groups of data and the corresponding parity check code from the plurality of first blocks; and writing the groups of data and the corresponding parity check code, read from the plurality of first blocks, to the at least one second block according to an order of storing the groups of data and the corresponding parity check code in the plurality of first blocks. ### Claim 19 A flash memory controller coupled to a flash memory module comprising a plurality of first blocks and at least one second block, and the flash memory controller comprises: a plurality of channels respectively connected to the flash memory module; and the flash memory controller is configured for: classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programing and RAID-like (Redundant Array of Independent Disks-like) RS (Reed-Solomon) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of first blocks; and when completing program of the plurality of first blocks, controlling the flash memory module to perform an internal copy operation to program the at least one second block of the flash memory module according to the plurality of first blocks of the flash memory module; a cell of one first block is used for storing a data amount which is smaller than a data amount stored by a cell of one second block.