# US 10,771,084 B2 · Double data rate interpolating analog to digital converter

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- Number: US 10,771,084 B2
- Document ID: US10771084B2
- Status: Granted
- Kind: B2
- Application number: 16/528,005
- Filed: 2019-07-31
- Published: 2019-11-21
- Granted: 2020-09-08
- Earliest claimed: 2017-01-31
- Assignees: Huawei Technologies Co., Ltd.
- Applicants: Huawei Technologies Co., Ltd.
- Inventors: Kimmo Koli
- Web page: https://patentgrep.com/patent/US10771084B2

## CPC

- H03M 1/206: {using a logic interpolation circuit}
- H03K 3/0233: Bistable circuits
- H04B 1/16: Circuits
- H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04B: TRANSMISSION
- H03F: AMPLIFIERS

## Abstract

A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core, and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle.

## Claims

### Claim 1

A double data rate comparator device, comprising:
a double data rate comparator core configured to compare a voltage of an input signal (IN) to a reference signal (REFN) during each of a rising edge and a falling edge in a single clock cycle of a clock input (CLK) to the double data rate comparator core, wherein the double data rate comparator core comprises a p-type metal-oxide-semiconductor (PMOS) differential amplifier stage and an n-type metal-oxide-semiconductor (NMOS) differential amplifier stage connected together in a push-pull configuration; and
a double data rate set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle, wherein the double data rate set-reset flip flop circuit comprises:
a set input (S); and
a reset input (R) connected to respective outputs (PN, MN) of the double data rate comparator core.

### Claim 2 (depends on 1)

The double data rate comparator device of claim 1, wherein the double data rate comparator core further comprises:
a first node (DM) connecting a first drain of the PMOS differential amplifier stage to a first drain of the NMOS differential amplifier stage; and
a second node (DP) connecting a second drain of the PMOS differential amplifier stage to a second drain of the NMOS differential amplifier stage, wherein a voltage at the first node (DM) and a voltage at the second node (DP) is charged towards a positive supply voltage (VDD) prior to the rising edge in the single clock cycle, wherein the voltage at the first node (DM) and the voltage at the second node (DP) is discharged towards a negative supply voltage (VSS) during the rising edge in the single clock cycle, and wherein the voltage at the first node (DM) and the voltage at the second node (DP) is charged towards the positive supply voltage (VDD) during the falling edge in the single clock cycle.

### Claim 3 (depends on 2)

The double data rate comparator device of claim 2, wherein a plus comparator core output (OUTP) of the double data rate comparator core is produced by a complementary metal-oxide-semiconductor (CMOS) inverter coupled to the first node (DM) and a minus comparator core output (OUTM) of the double data rate comparator core is produced by a second CMOS inverter coupled to the second node (DP), and wherein a timing of the plus comparator core output (OUTP) and the minus comparator core output (OUTM) is proportional to a voltage difference between the input signal (IN) and the reference signal (REFN).

### Claim 4 (depends on 1)

The double data rate comparator device of claim 1, wherein the double data rate set-reset flip flop circuit comprises:
a first set-reset (SR) latch circuit connected in parallel with a second SR latch circuit;
a third SR latch circuit;
a switching device configured to selectively connect outputs of the first SR latch circuit; and
a controller configured to control the switching device to switch between the outputs of the first SR latch circuit and the outputs of the second SR latch circuit in response to a state of a signal on the set input (S) and a state of a signal on the reset input (R) to the double data rate set-reset flip flop circuit being equal.

### Claim 5 (depends on 4)

The double data rate comparator device of claim 4, wherein a set input and a reset input of the first SR latch circuit are connected to the respective outputs (PN, MN) of the double data rate comparator core, and wherein a set input and a reset input of the second SR latch circuit are connected to inverted forms of the respective outputs (PN, MN) of the double data rate comparator core.

### Claim 6 (depends on 4)

The double data rate comparator device of claim 4, wherein the set input of the first SR latch circuit is connected to a set input node (S) of the set-reset circuit, wherein the reset input of the first SR latch circuit is connected to a reset input node (R) of the set-reset circuit, wherein the reset input of the second SR latch circuit is connected to an output of an inverter connected between the set input node (S) and the reset input, wherein the set input of the second SR latch circuit is connected to an output of an inverter connected between the reset input node (R) and the set input, and wherein the switching device is configured to selectively connect a first input of the third SR latch circuit and a second input of the third SR latch circuit to first and second outputs of the first SR latch circuit and the first and second outputs of the second SR latch circuit.

### Claim 7 (depends on 4)

The double data rate comparator device of claim 4, wherein the controller comprises a first input connected to a set (S) input node of the set-reset circuit, a second input connected to a reset (R) node of the set-reset circuit, and an output connected to a switching control input of the switching device.

### Claim 8 (depends on 1)

The double data rate comparator device of claim 1, wherein the double data rate set-reset flip flop circuit comprises:
a first set-reset (SR) latch circuit connected in parallel with a second SR latch circuit;
a third SR latch circuit;
a switching device configured to selectively connect outputs of the second SR latch circuit to respective inputs of the third SR latch circuit; and
a controller configured to control the switching device to switch between the outputs of the first SR latch circuit and the outputs second SR latch circuit in response to a state of a signal on the set input (S) and a state of a signal on the reset input (R) to the set-reset circuit being equal.

### Claim 9 (depends on 1)

The double data rate comparator device of claim 1, wherein the double data rate comparator core further comprises:
a first node (DM) connecting a first drain of the PMOS differential amplifier stage to a first drain of the NMOS differential amplifier stage; and
a second node (DP) connecting a second drain of the PMOS differential amplifier stage to a second drain of the NMOS differential amplifier stage.

### Claim 10

A radio receiver comprising:
a double data rate comparator device, comprising:
a double data rate comparator core configured to compare a voltage of an input signal (IN) to a reference signal (REFN) during each of a rising edge and a falling edge in a single clock cycle of a clock input (CLK) to the double data rate comparator core, wherein the double data rate comparator core comprises a p-type metal-oxide-semiconductor (PMOS) differential amplifier stage and a n-type metal-oxide-semiconductor (NMOS) differential amplifier stage connected together in a push-pull configuration; and
a double data rate set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle, wherein the double data rate set-reset flip flop circuit comprises:
a set input (S); and
a reset input (R) connected to respective outputs (PN, MN) of the double data rate comparator core.

### Claim 11 (depends on 10)

The radio receiver of claim 10, wherein the double data rate comparator core further comprises:
a first node (DM) connecting a first drain of the PMOS differential amplifier stage to a first drain of the NMOS differential amplifier stage; and
a second node (DP) connecting a second drain of the PMOS differential amplifier stage to a second drain of the NMOS differential amplifier stage, wherein a voltage at the first node (DM) and a voltage at the second node (DP) is charged towards a positive supply voltage (VDD) prior to the rising edge in the single clock cycle, wherein the voltage at the first node (DM) and the voltage at the second node (DP) is discharged towards a negative supply voltage (VSS) during the rising edge in the single clock cycle, and wherein the voltage at the first node (DM) and the voltage at the second node (DP) is charged towards the positive supply voltage (VDD) during the falling edge in the single clock cycle.

### Claim 12 (depends on 11)

The radio receiver of claim 11, wherein a plus comparator core output (OUTP) of the double data rate comparator core is produced by a complementary metal-oxide-semiconductor (CMOS) inverter coupled to the first node (DM) and a minus comparator core output (OUTM) of the double data rate comparator core is produced by a second CMOS inverter coupled to the second node (DP), and wherein a timing of the plus comparator core output (OUTP) and the minus comparator core output (OUTM) is proportional to a voltage difference between the input signal (IN) and the reference signal (REFN).

### Claim 13 (depends on 10)

The radio receiver of claim 10, wherein the double data rate comparator core further comprises:
a first node (DM) connecting a first drain of the PMOS differential amplifier stage to a first drain of the NMOS differential amplifier stage; and
a second node (DP) connecting a second drain of the PMOS differential amplifier stage to a second drain of the NMOS differential amplifier stage.

### Claim 14

A double data rate interpolating analog-to-digital converter comprising:
a first double data rate comparator device;
a second double data rate comparator device; and
a first two-stage interpolator block, comprising:
a first stage comprising a double data rate time-based interpolator block configured to:
receive a first lower input signal and a first upper input signal, wherein the first lower input signal is connected to one of a minus output or a plus output of the first double data rate comparator device, and the first upper input signal is connected to a corresponding one of a minus output or a plus output of the second double data rate comparator device; and
produce an interpolator output signal, wherein a slope change of the interpolator output signal is linearly related to a timing between the first lower input signal and the first upper input signal; and
a second stage comprising a first plurality of complementary metal-oxide-semiconductor (CMOS) inverters, wherein each CMOS inverter is configured to:
receive the interpolator output signal; and
produce a delayed inverter output signal.

### Claim 15 (depends on 14)

The double data rate interpolating analog-to-digital converter of claim 14, wherein the double data rate time-based interpolator block comprises:
a first p-type metal-oxide-semiconductor (PMOS) switching leg and a second PMOS switching leg connected in parallel between a positive supply voltage (VDD) and the interpolator output signal;
a first n-type metal-oxide-semiconductor (NMOS) switching leg and a second NMOS switching leg connected in parallel between a negative supply voltage (VS S) and the interpolator output signal; and
a controller configured to:
receive a clock signal; and
produce a first control signal and a second control signal, wherein the first control signal is coupled to the first and second PMOS switching legs and the second control signal is coupled to the first and second NMOS switching legs, wherein the first control signal is configured to disable the first and second PMOS switching legs after a falling edge in the clock signal, and wherein the second control signal is configured to disable the first and second NMOS switching legs after a rising edge in the clock signal.

### Claim 16 (depends on 15)

The double data rate interpolating analog-to-digital converter of claim 15, wherein the first PMOS switching leg and the first NMOS switching leg of the double data rate time-based interpolator block are connected to the first upper input signal, and the second PMOS switching leg and the second NMOS switching leg of the double data rate time-based interpolator block are connected to the first lower input signal.

### Claim 17 (depends on 15)

The double data rate interpolating analog-to-digital converter of claim 15, wherein the controller of the double data rate time-based interpolator block is configured to receive a pair of enable signals, and wherein deactivating the pair of enable signals disables both the first and second PMOS switching legs and the first and second NMOS switching legs.

### Claim 18 (depends on 14)

The double data rate interpolating analog-to-digital converter of claim 14, further comprising a second two-stage interpolator block comprising the first stage and the second stage, wherein the second two-stage interpolator block is configured to:
receive a second lower input and a second upper input, wherein the second lower input and the second upper input are both connected to a common output of the first double data rate comparator device; and
generate a second plurality of delayed inverter outputs, wherein a first delayed inverter output generated by the first two-stage interpolator block is coupled to a second delayed interpolator output generated by the second two-stage interpolator block.

### Claim 19 (depends on 18)

The double data rate interpolating analog-to-digital converter of claim 18, further comprising a plurality of double data rate set-reset flip flop circuits, wherein the second plurality of delayed inverter outputs is generated by a second plurality of CMOS inverters, wherein each CMOS inverter in both the first plurality of CMOS inverters and the second plurality of CMOS inverters comprises one or more unit inverters, wherein a set-reset flip flop circuit in a plurality of set-reset flip flop circuits is connected to one CMOS inverter in the first plurality of CMOS inverters and to one CMOS inverter in the second plurality of CMOS inverters, and wherein a same number of unit inverters are connected to each set-reset flip flop circuit.

### Claim 20 (depends on 14)

The double data rate interpolating analog-to-digital converter of claim 14, wherein each of the first double data rate comparator device and the second double data rate comparator device comprises:
a double data rate comparator core configured to compare a voltage of an input signal (IN) to a reference signal (REFN) during each of a rising edge and a falling edge in a single clock cycle of a clock input (CLK) to the double data rate comparator core; and
a double data rate set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle, wherein the double data rate set-reset flip flop circuit comprises:
a set input (S); and
a reset input (R) connected to respective outputs (PN, MN) of the double data rate comparator core.