# US 10,771,082 B1 · Circuitry for low input charge analog to digital conversion

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- Number: US 10,771,082 B1
- Document ID: US10771082B1
- Status: Granted
- Kind: B1
- Application number: 16/560,683
- Filed: 2019-09-04
- Granted: 2020-09-08
- Earliest claimed: 2019-09-04
- Assignees: STMicroelectronics International N.V.
- Applicants: STMicroelectronics International N.V.
- Inventors: Rajesh Narwal; Kavindu Shekhar Benjwal
- Web page: https://patentgrep.com/patent/US10771082B1

## CPC

- G11C 27/024: {using a capacitive memory element (G11C27/04 takes precedence)}
- H03M 1/1245: {Details of sampling arrangements or methods}
- H03K 3/037: Bistable circuits
- H03M 1/122: {Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages}
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An analog-to-digital converter includes a sampling capacitor connected to a multiplexer output, discharge circuitry discharging the sampling capacitor during a first period beginning at a start of a sampling cycle, and level shifting circuitry charging the sampling capacitor to a voltage at a first analog input node modified by a mismatch voltage resulting from mismatch in threshold voltages between a first transistor connected to the first analog input node and a second transistor connected to the output node, during a second period beginning at expiration of the first period. A first switch connects the first analog input node to the output node to charge the sampling capacitor to the voltage at the first analog input node, at expiration of the second period, and disconnects the first analog input node from the output node at an end of the sampling cycle of the analog-to-digital converter.

## Claims

### Claim 1

An input circuit for a multiplexer, the input circuit comprising:
a first analog input node;
an output node;
a capacitive node connected to the output node;
a first control circuit configured to set a charge at the capacitive node to a desired voltage during a first period of time beginning in response to a start of a sampling cycle of an analog to digital converter where input to the analog to digital converter is driven by output from the multiplexer;
a second control circuit configured to set a charge at the capacitive node to a voltage at the first analog input node, modified by a mismatch voltage resulting from mismatch in threshold voltages between a first transistor connected to the first analog input node and a second transistor connected to the output node, during a second period of time beginning in response to expiration of the first period of time; and
a first channel selection switch that closes to connect the first analog input node to the output node to thereby charge the capacitive node to the voltage at the first analog input node, the first channel selection switch being closed in response to expiration of the second period of time;
wherein the first channel selection switch opens to disconnect the first analog input node from the output node at an end of the sampling cycle of the analog to digital converter.

### Claim 2 (depends on 1)

The input circuit of claim 1, wherein the first control circuit comprises discharge circuitry configured to discharge the capacitive node to ground during the first period of time; wherein the second control circuit comprises level shifting circuitry configured to charge the capacitive node to the voltage at the first analog input node, modified by the mismatch voltage resulting from the mismatch in threshold voltages between the first transistor and the second transistor, during the second period of time; and wherein the level shifting circuitry includes the first transistor and the second transistor.

### Claim 3 (depends on 2)

The input circuit of claim 2, further comprising a control signal generator configured to:
assert a second control signal, for the first period of time, in response to the start of the sampling cycle of the analog to digital converter;
deassert the second control signal in response to the expiration of the first period of time;
assert a first control signal, for the second period of time, in response to the expiration of the first period of time; and
deassert the first control signal in response to the expiration of the second period of time.

### Claim 4 (depends on 3)

The input circuit of claim 3,
wherein the first transistor comprises a first p-channel transistor having a drain connected to ground, a source connected to a first node, and a gate connected to the first analog input node;
wherein the second transistor comprises a second n-channel transistor having a source connected to the output node and a gate connected to a second node; and
wherein the level shifting circuitry further comprises:
a first n-channel transistor having a drain connected to the second node, a source connected to ground, and a gate connected to the first control signal;
a transmission gate configured to connect the first node to the second node in response to assertion of the first control signal;
a second p-channel transistor having a drain connected to a drain of the second n-channel transistor, a source connected to a supply voltage, and a gate connected to the first control signal;
a logic gate configured to generate a logic signal as a function of a logical operation performed on the second control signal and a complement of the first control signal;
a resistor having a first terminal connected to the first node; and
a third p-channel transistor having a drain connected to a second terminal of the resistor, a source connected pled to the supply voltage, and a gate connected to the logic signal.

### Claim 5 (depends on 4)

The input circuit of claim 4, wherein the logic gate comprises a NOR gate receiving the second control signal and a complement of the first control signal as input, and generating the logic signal as output.

### Claim 6 (depends on 4)

The input circuit of claim 4, wherein the discharge circuitry comprises a third n-channel transistor having a drain connected to the output node, a source connected to ground, and a gate connected to the second control signal.

### Claim 7 (depends on 2)

The input circuit of claim 2, further comprising:
a second analog input node;
second discharge circuitry configured to discharge the capacitive node during the first period of time;
second level shifting circuitry configured to charge the capacitive node to a voltage at the second analog input node, modified by a mismatch voltage resulting from mismatch in threshold voltages between a third transistor connected to the second analog input node and a fourth transistor connected to the output node, during the second period of time; and
a second channel selection switch that closes to connect the second analog input node to the output node to thereby charge the capacitive node to the voltage at the second analog input node, the second channel selection switch being closed in response to expiration of the second period of time;
wherein the second channel selection switch opens to disconnect the second analog input node from the output node at the end of the sampling cycle of the analog to digital converter;
wherein the first channel selection switch operates based upon a first channel selection signal that is asserted in response to expiration of the second period of time and deasserted at the end of the sampling cycle of the analog to digital converter if a first channel including the first analog input node, discharge circuitry, level shifting circuitry, and first channel selection switch is selected; and
wherein the second channel selection switch operates based upon a second channel selection signal that is asserted in response to expiration of the second period of time and deasserted at the end of the sampling cycle of the analog to digital converter if a second channel including the second analog input node, second discharge circuitry, second level shifting circuitry, and second channel selection switch is selected.

### Claim 8 (depends on 1)

The input circuit of claim 1, wherein the first control circuit comprises charge circuitry configured to charge the capacitive node to a supply voltage, during the first period of time; wherein the second control circuit comprises level shifting circuitry configured to discharge the capacitive node to the voltage at the first analog input node, modified by the mismatch voltage resulting from the mismatch in threshold voltages between the first transistor and the second transistor, during the second period of time;
and wherein the level shifting circuitry includes the first transistor and the second transistor.

### Claim 9 (depends on 8)

The input circuit of claim 8, further comprising a control signal generator configured to:
assert a second control signal, for the first period of time, in response to the start of the sampling cycle of the analog to digital converter;
deassert the second control signal in response to the expiration of the first period of time;
assert a first control signal, for the second period of time, in response to the expiration of the first period of time; and
deassert the first control signal in response to the expiration of the second period of time.

### Claim 10 (depends on 9)

The input circuit of claim 9,
wherein the first transistor comprises a first n-channel transistor having a drain connected to the supply voltage, a source connected to a first node, and a gate connected to the first analog input node;
wherein the second transistor comprises a second p-channel transistor having a source connected to the output node and a gate connected to a second node; and
wherein the level shifting circuitry comprises:
a first p-channel transistor having a source connected to the supply voltage, a drain connected to the second node, and a gate connected to a complement of the first control signal;
a second n-channel transistor having a drain connected to a drain of the second p-channel transistor, a source connected to ground, and a gate connected to the complement of the first control signal;
a logic gate configured to generate a logic signal as a function of a logical operation performed on the second control signal and the first control signal;
a resistor having a first terminal connected to the first node; and
a third n-channel transistor having a drain connected to a second terminal of the resistor, a source connected to ground, and a gate connected to the logic signal.

### Claim 11 (depends on 10)

The input circuit of claim 10, wherein the logic gate comprises a NAND gate receiving the first and second control signals as input and generating the logic signal as output.

### Claim 12 (depends on 10)

The input circuit of claim 10, wherein the charge circuitry comprises a third p-channel transistor having a source connected to the supply voltage, a drain connected to the output node, and a gate connected to the second control signal.

### Claim 13 (depends on 8)

The input circuit of claim 8, further comprising:
a second analog input node;
second charge circuitry configured to charge the capacitive node to the supply voltage, during the first period of time;
second level shifting circuitry configured to discharge the capacitive node to the voltage at the second analog input node, modified by a mismatch voltage resulting from mismatch in threshold voltages between a third transistor connected to the second analog input node and a fourth transistor connected to the output node, during the second period of time; and
a second channel selection switch that closes to connect the second analog input node to the output node to thereby charge the capacitive node to the voltage at the second analog input node, the second channel selection switch being closed in response to expiration of the second period of time;
wherein the second channel selection switch opens to disconnect the second analog input node from the output node at an end of the sampling cycle of the analog to digital converter;
wherein the first channel selection switch operates based upon a first channel selection signal that is asserted in response to expiration of the second period of time and deasserted at the end of the sampling cycle of the analog to digital converter if a first channel including the first analog input node, charge circuitry, level shifting circuitry, and first channel selection switch is selected; and
wherein the second channel selection switch operates based upon a second channel selection signal that is asserted in response to expiration of the second period of time and deasserted at the end of the sampling cycle of the analog to digital converter if a second channel including the second analog input node, second charge circuitry, second level shifting circuitry, and second channel selection switch is selected.

### Claim 14

An input circuit for an analog to digital converter, the input circuit comprising:
a first channel selection switch that closes to connect a first analog input node to an intermediate node to thereby charge the intermediate node to a voltage at the first analog input node, the first channel selection switch being closed during a first period of time beginning in response to a start of a sampling cycle of the analog to digital converter;
a capacitive node connected to an output node;
discharge circuitry connected between the first channel selection switch and the output node and configured to discharge the capacitive node during the first period of time;
level shifting circuitry configured to charge the capacitive node to a voltage at the intermediate node less a threshold voltage of a first transistor of the level shifting circuitry during a second period of time beginning in response to expiration of the first period of time; and
a selection switch that closes to connect the intermediate node to the output node to thereby charge the output node to the voltage at the intermediate node, the selection switch being closed in response to expiration of the second period of time;
wherein the selection switch opens to disconnect the intermediate node from the output node at an end of the sampling cycle of the analog to digital converter.

### Claim 15 (depends on 14)

The input circuit of claim 14, further comprising:
a control signal generator configured to:
assert a second control signal for a first period of time, in response to a start of the sampling cycle of the analog to digital converter;
deassert the second control signal in response to an end of the first period of time;
assert a first control signal, for a second period of time, in response to the end of the first period of time; and
deassert the first control signal in response to an end of the second period of time.

### Claim 16 (depends on 15)

The input circuit of claim 15,
wherein the first transistor is within the level shifting circuitry and comprises a first n-channel transistor having a source connected to the output node and a gate connected to the intermediate node; and
wherein the level shifting circuitry further comprises a first p-channel transistor having a source connected to a supply voltage, a drain connected to a drain of the first n-channel transistor, and a gate connected to the first control signal.

### Claim 17 (depends on 16)

The input circuit of claim 16, wherein the discharge circuitry comprises a second n-channel transistor having a drain connected to the output node, a source connected to ground, and a gate connected to the second control signal.

### Claim 18 (depends on 14)

The input circuit of claim 14, further comprising:
a second channel selection switch that closes to connect a second analog input node to the intermediate node to thereby charge the intermediate node to a voltage at the second analog input node, the second channel selection switch being closed during the first period of time;
wherein the first channel selection switch operates based upon a first channel selection signal that is asserted in response to expiration of the second period of time and deasserted at the end of the sampling cycle of the analog to digital converter if a first channel including the first analog input node, discharge circuitry, level shifting circuitry, and first channel selection switch is selected; and
wherein the second channel selection switch operates based upon a second channel selection signal that is asserted in response to expiration of the second period of time and deasserted at the end of the sampling cycle of the analog to digital converter if a second channel including the second analog input node, second discharge circuitry, second level shifting circuitry, and second channel selection switch is selected.

### Claim 19

An input circuit for an analog to digital converter, the input circuit comprising:
a first channel selection switch that closes to connect a first analog input node to an intermediate node to thereby charge the intermediate node to a voltage at the first analog input node, the first channel selection switch being closed during a first period of time beginning in response to a start of a sampling cycle of the analog to digital converter;
a capacitive node connected to an output node;
charge circuitry connected between the first channel selection switch and the output node and configured to charge the capacitive node to a supply voltage during the first period of time;
level shifting circuitry configured to discharge the capacitive node to a voltage at the intermediate node plus a threshold voltage of a first transistor of the level shifting circuitry during a second period of time beginning in response to expiration of the first period of time; and
a selection switch that closes to connect the intermediate node to the output node to thereby discharge the output node to the voltage at the intermediate node, the selection switch being closed in response to expiration of the second period of time;
wherein the selection switch opens to disconnect the intermediate node from the output node at an end of the sampling cycle of the analog to digital converter.

### Claim 20 (depends on 19)

The input circuit of claim 19, further comprising:
a control signal generator configured to:
assert a second control signal, for a first period of time, in response to a start of the sampling cycle of the analog to digital converter;
deassert the second control signal in response to an end of the first period of time;
assert a first control signal, for a second period of time, in response to the end of the first period of time; and
deassert the first control signal in response to an end of the second period of time.

### Claim 21 (depends on 20)

The input circuit of claim 20,
wherein the first transistor is within the level shifting circuitry and comprises a first p-channel transistor having a source connected to the output node and a gate connected to the intermediate node; and
wherein the level shifting circuitry further comprises a first n-channel transistor having a drain connected to a drain of the first p-channel transistor, a source connected to ground, and a gate connected to the first control signal.

### Claim 22 (depends on 21)

The input circuit of claim 21, wherein the charge circuitry comprises a second p-channel transistor having a drain connected to the output node, a source connected to the supply voltage, and a gate connected to the second control signal.

### Claim 23 (depends on 19)

The input circuit of claim 19, further comprising:
a second channel selection switch that closes to connect a second analog input node to the intermediate node to thereby discharge the intermediate node to a voltage at the second analog input node, the second channel selection switch being closed during the first period of time;
wherein the first channel selection switch operates based upon a first channel selection signal that is asserted in response to expiration of the second period of time and deasserted at the end of the sampling cycle of the analog to digital converter if a first channel including the first analog input node, discharge circuitry, level shifting circuitry, and first channel selection switch is selected; and
wherein the second channel selection switch operates based upon a second channel selection signal that is asserted in response to expiration of the second period of time and deasserted at the end of the sampling cycle of the analog to digital converter if a second channel including the second analog input node, second discharge circuitry, second level shifting circuitry, and second channel selection switch is selected.

### Claim 24

An input circuit for an analog to digital converter, the input circuit comprising:
a first channel selection switch that closes to connect a first analog input node to an intermediate node to thereby charge the intermediate node to a voltage at the first analog input node, the first channel selection switch being closed during a first period of time beginning in response to a start of a sampling cycle of the analog to digital converter;
a capacitive node connected to an output node;
a first control circuit connected between the first channel selection switch and the output node and configured to set a charge at the capacitive node to a desired voltage during the first period of time;
a second control circuit configured to set a charge at the capacitive node to a voltage at the intermediate node, modified by a mismatch voltage resulting from mismatch in threshold voltages between a first transistor connected to the intermediate node and a second transistor connected to the output node, during a second period of time beginning in response to expiration of the first period of time; and
a selection switch that closes to connect the intermediate node to the output node to thereby charge the output node to the voltage at the intermediate node, the selection switch being closed in response to expiration of the second period of time;
wherein the selection switch opens to disconnect the intermediate node from the output node at an end of the sampling cycle of the analog to digital converter.

### Claim 25 (depends on 24)

The input circuit of claim 24, wherein the first control circuit comprises a discharge circuitry connected between the first channel selection switch and the output node and configured to discharge the capacitive node during the first period of time; and wherein the second control circuit comprises level shifting circuitry configured to charge the capacitive node to the voltage at the intermediate node modified by the mismatch voltage during the second period of time.

### Claim 26 (depends on 25)

The input circuit of claim 25, further comprising:
a control signal generator configured to:
assert a second control signal, for a first period of time, in response to a start of the sampling cycle of the analog to digital converter;
deassert the second control signal in response to an end of the first period of time;
assert a first control signal, for a second period of time, in response to the end of the first period of time; and
deassert the first control signal, in response to an end of the second period of time.

### Claim 27 (depends on 26)

The input circuit of claim 26,
wherein the first transistor comprises a first p-channel transistor having a source connected to a first node, a drain connected to ground, and a gate connected to the intermediate node;
wherein the second transistor comprises a second n-channel transistor having a source connected to the output node and a gate connected to a second node; and
wherein the level shifting circuitry comprises:
a first n-channel transistor having a drain connected to the second node, a source connected to ground, and a gate connected to the first control signal;
a second p-channel transistor having a source connected led to a supply voltage, a drain connected to a drain of the first n-channel transistor, and a gate connected to the first control signal;
a logic gate configured to generate a logic signal as a function of a logical operation performed on the second control signal and a complement of the first control signal;
a resistor having a first terminal connected to the first node;
a third p-channel transistor having a source connected to the supply voltage, a drain connected to a second terminal of the resistor, and a gate connected to the logic signal; and
a transmission gate configured to connect the first node to the second node in response to assertion of the first control signal.

### Claim 28 (depends on 27)

The input circuit of claim 27, wherein the discharge circuitry comprises a third n-channel transistor having a drain connected to the output node, a source connected to ground, and a gate connected to the second control signal.

### Claim 29 (depends on 27)

The input circuit of claim 27, wherein the logic gate comprises a NOR gate receiving the second control signal and a complement of the first control signal as input, and generating the logic signal as output.

### Claim 30 (depends on 25)

The input circuit of claim 25, further comprising:
a second channel selection switch that closes to connect a second analog input node to the intermediate node to thereby charge the intermediate node to a voltage at the second analog input node, the second channel selection switch being closed during the first period of time;
wherein the first channel selection switch operates based upon a first channel selection signal that is asserted in response to expiration of the second period of time and deasserted at the end of the sampling cycle of the analog to digital converter if a first channel including the first analog input node, discharge circuitry, level shifting circuitry, and first channel selection switch is selected; and
wherein the second channel selection switch operates based upon a second channel selection signal that is asserted in response to expiration of the second period of time and deasserted at the end of the sampling cycle of the analog to digital converter if a second channel including the second analog input node, second discharge circuitry, second level shifting circuitry, and second channel selection switch is selected.

### Claim 31 (depends on 25)

The input circuit of claim 25, wherein the first control circuit comprises charge circuitry connected between the first channel selection switch and the output node and configured to charge the capacitive node to a supply voltage during the first period of time; and
wherein the second control circuit comprises level shifting circuitry configured to discharge the capacitive node to the voltage at the intermediate node modified by the mismatch voltage during the second period of time.

### Claim 32 (depends on 31)

The analog to digital converter of claim 31, further comprising:
a control signal generator configured to:
assert a second control signal, for a first period of time, in response to a start of a sampling cycle of the analog to digital converter;
deassert the second control signal in response to an end of the first period of time;
assert a first control signal, for a second period of time, in response to the end of the first period of time; and
deassert the first control signal in response to an end of the second period of time.

### Claim 33 (depends on 32)

The analog to digital converter of claim 32,
wherein the first transistor comprises a first n-channel transistor having a drain connected to the supply voltage, a source connected to a first node, and a gate connected to the intermediate node;
wherein the second transistor comprises a second p-channel transistor having a source connected to the output node and a gate connected to a second node;
a transmission gate connecting the first node to the second node in response to assertion of the first control signal; and
wherein the level shifting circuitry comprises:
a first p-channel transistor having a source connected to the supply voltage, a drain connected to the second node, and a gate connected to a complement of the first control signal;
a second n-channel transistor having a drain connected to a drain of the second p-channel transistor, a source connected to ground, and a gate connected to the complement of the first control signal;
a logic gate generating a logic signal based upon a logical operation performed on the first and second control signals;
a resistor having a first terminal connected to a source of the first n-channel transistor; and
a third n-channel transistor having a drain connected to a second terminal of the resistor, a source connected to ground, and a gate connected to the logic signal.

### Claim 34 (depends on 33)

The analog to digital converter of claim 33, wherein the logic gate comprises a NAND gate receiving input from the first and second control signals and generating the logic signal as output.

### Claim 35 (depends on 33)

The analog to digital converter of claim 33, wherein the charge circuitry comprises a third p-channel transistor having a source connected to the supply voltage, a drain connected to the output node, and a gate connected to the second control signal.

### Claim 36 (depends on 31)

The analog to digital converter of claim 31, further comprising:
a second channel selection switch that closes to connect a second analog input node to the intermediate node to thereby charge the intermediate node to a voltage at the second analog input node during the first period of time;
wherein the first channel selection switch operates based upon a first channel selection signal that is asserted in response to expiration of the second period of time and deasserted at the end of the sampling cycle of the analog to digital converter if a first channel including the first analog input node, discharge circuitry, level shifting circuitry, and first channel selection switch is selected; and
wherein the second channel selection switch operates based upon a second channel selection signal that is asserted in response to expiration of the second period of time and deasserted at the end of the sampling cycle of the analog to digital converter if a second channel including the second analog input node, second discharge circuitry, second level shifting circuitry, and second channel selection switch is selected.