# US 10,771,078 B2 · Comparator offset calibration system and analog-to-digital converter with comparator offset calibration

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,771,078 B2
- Document ID: US10771078B2
- Status: Granted
- Kind: B2
- Application number: 16/378,759
- Filed: 2019-04-09
- Published: 2019-11-21
- Granted: 2020-09-08
- Earliest claimed: 2018-05-15
- Assignees: Mediatek Inc.
- Applicants: Mediatek Inc.
- Inventors: Chun-Cheng Liu
- Web page: https://patentgrep.com/patent/US10771078B2

## CPC

- H03M 1/1023: {Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295)}
- H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)}
- H03F 3/45744: {by offset reduction}
- H03H 19/004: {Switched capacitor networks}
- H03M 1/0607: {Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295)}
- H03M 1/109: {for DC performance, i.e. static testing (H03M1/1085 takes precedence)}
- H03M 1/121: {Interleaved, i.e. using multiple converters or converter parts for one channel}
- H03M 1/34: Analogue value compared with reference values (H03M1/48 takes precedence)
- H03F 2203/45048: Calibrating and standardising a dif amp
- H03M 1/1009: {Calibration}
- H03M 1/12: Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence)
- H03M 3/38: {Calibration}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03F: AMPLIFIERS
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)

## Abstract

A comparator offset calibration system having a comparator offset evaluator and a switched-capacitor network is disclosed, which is in an analog and digital dual domain structure. The comparator offset evaluator receives digital data from an analog-to-digital conversion module, evaluates an offset of a comparator of the analog-to-digital conversion module based on the received digital data, and outputs an evaluated result. The switched-capacitor network processes the evaluated result to generate a control signal. The analog-to-digital conversion module adjusts the offset of the comparator according to the control signal.

## Claims

### Claim 1

A comparator offset calibration system, comprising:
a comparator offset evaluator, receiving digital data from an analog-to-digital conversion module which comprises a comparator, evaluating an offset of the comparator based on the received digital data, and outputting an evaluated result; and
a switched-capacitor network, processing the evaluated result to generate a control signal,
wherein:
the comparator offset evaluator outputs the evaluated result in a pulse width modulation form;
the comparator offset evaluator evaluates the offset of the comparator by long-term judgment of the received digital data; and
the analog-to-digital conversion module adjusts the offset of the comparator according to the control signal.

### Claim 2 (depends on 1)

The comparator offset calibration system as claimed in claim 1, wherein:
the comparator offset evaluator uses an accumulation module to transform a series of judgment values obtained by the long-term judgment to the evaluated result that is in the pulse width modulation form; and
the evaluated result in the pulse width modulation form is retrieved from a carry-out output of the accumulation module.

### Claim 3 (depends on 2)

The comparator offset calibration system as claimed in claim 2, wherein:
the comparator offset evaluator repeats mean value calculation on the received digital data periodically to generate a series of mean values and performs mean value judgment on the series of mean values.

### Claim 4 (depends on 3)

The comparator offset calibration system as claimed in claim 3, wherein:
the comparator offset evaluator performs the mean value judgment by comparing the series of mean values with a reference value and thereby generates the series of judgment values.

### Claim 5 (depends on 4)

The comparator offset calibration system as claimed in claim 4, wherein:
the digital data is N bits, where N is a number; and
the reference value is (2N−1)/2.

### Claim 6 (depends on 1)

The comparator offset calibration system as claimed in claim 1, further comprising:
a calibration circuit provided within the analog-to-digital conversion module,
wherein:
the comparator has an input pair;
the calibration circuit is an auxiliary input pair provided for the comparator, and the auxiliary input pair receives the control signal; and
the control signal is in a differential form.

### Claim 7 (depends on 6)

The comparator offset calibration system as claimed in claim 6, wherein:
the switched-capacitor network uses a first switched-capacitor filter and a second switched-capacitor filter to generate the control signal that is in the differential form.

### Claim 8 (depends on 7)

The comparator offset calibration system as claimed in claim 7, wherein:
the comparator offset evaluator obtains a first series of judgment values and a second series of judgment values by the long-term judgment;
the comparator offset evaluator uses a first accumulator to accumulate the first series of judgment values and uses a second accumulator to accumulate the second series of judgment values; and
a first carry out bit of the first accumulator is coupled to the first switched-capacitor filter and a second carry out bit of the second accumulator is coupled to the second switched-capacitor filter.

### Claim 9 (depends on 8)

The comparator offset calibration system as claimed in claim 8, wherein:
the comparator offset evaluator repeats mean value calculation on the received digital data periodically to generate a series of mean values and performs mean value judgment on the series of mean values.

### Claim 10 (depends on 9)

The comparator offset calibration system as claimed in claim 9, wherein:
the comparator offset evaluator performs the mean value judgment by comparing the series of mean values with a reference value and thereby generates the first series of judgment values and the second series of judgment values.

### Claim 11 (depends on 10)

The comparator offset calibration system as claimed in claim 10, wherein:
the digital data is N bits, where N is a number; and
the reference value is (2N−1)/2.

### Claim 12 (depends on 8)

The comparator offset calibration system as claimed in claim 8, wherein:
the first accumulator and the second accumulator operate according to a first clock;
the first switched-capacitor filter and the second switched-capacitor filter operate according to the first clock and a second clock; and
the second clock has non-overlapped activation intervals with the first clock.

### Claim 13 (depends on 7)

The comparator offset calibration system as claimed in claim 7, wherein:
the first switched-capacitor filter and the second switched-capacitor filter are multi-stage filters.

### Claim 14 (depends on 1)

The comparator offset calibration system as claimed in claim 1, wherein:
the comparator offset evaluator down-samples the received digital data to ease the long-term judgment.

### Claim 15

An analog-to-digital converter, comprising:
an analog-to-digital conversion module, comprising at least one comparator;
a comparator offset evaluator, receiving digital data from the analog-to-digital conversion module, evaluating an offset of the at least one comparator based on the received digital data, and outputting evaluated result; and
a switched-capacitor network, processing the evaluated result to generate a control signal,
wherein:
the analog-to-digital conversion module adjusts the offset of the comparator according to the control signal,
the analog-to-digital conversion module comprises a first comparator and a second comparator; and
the first comparator and the second comparator share the comparator offset evaluator and the switched-capacitor network.