# US 10,771,077 B1 · Hybrid return-to-zero voltage-mode DAC driver > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,771,077 B1 - Document ID: US10771077B1 - Status: Granted - Kind: B1 - Application number: 16/354,512 - Filed: 2019-03-15 - Granted: 2020-09-08 - Earliest claimed: 2019-03-15 - Assignees: Marvell Asia Pte Ltd - Applicants: Aquantia Corporation - Inventors: Joseph Briaire - Web page: https://patentgrep.com/patent/US10771077B1 ## CPC - H03M 1/0863: {of switching transients, e.g. glitches} - H03M 1/661: {Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing} - H03M 1/662: {Multiplexed conversion systems} - H03M 1/742: {using current sources as quantisation value generators} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A voltage-mode digital-to-analog converter (DAC) includes multiple bit processing circuits to generate an output voltage responsive to a binary input. Each of the multiple bit processing circuits includes a first switch circuit and a second switch circuit. The first switch circuit is to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time. The first output load has a value proportional to d. The second switch circuit is to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time. The second output load has a value corresponding to the first output load. The first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to (1-d). ## Claims ### Claim 1 A voltage-mode digital-to-analog converter (DAC), comprising: multiple bit processing circuits to generate an output voltage responsive to a binary input, each of the multiple bit processing circuits including a first switch circuit to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time, the first output load having a value proportional to a scaling value d, a second switch circuit to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time, the second output load having a value corresponding to the first output load, and wherein the first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to a relationship (1-d). ### Claim 2 (depends on 1) The voltage-mode DAC according to claim 1, wherein the first and second switch circuits each comprise push-pull voltage-mode sub-drivers. ### Claim 3 (depends on 1) The voltage-mode DAC according to claim 1, wherein the scaling value d comprises a selectable value between 0 and 1 such that the first and second output loads cooperate to exhibit hybrid direct driver and split driver characteristics. ### Claim 4 (depends on 1) The voltage-mode DAC according to claim 1, wherein the first and second switching circuits are sequenced during the first and second bit times in accordance with a return-to-zero protocol. ### Claim 5 (depends on 1) The voltage-mode DAC according to claim 1, further comprising: a current-steering output stage coupled to the third output load. ### Claim 6 (depends on 5) The voltage-mode DAC according to claim 5, wherein the current-steering output stage includes tunable current source/sink circuitry to compensate for common-mode data signals. ### Claim 7 (depends on 1) The voltage-mode DAC according to claim 1, wherein the first and second switch circuits alternatingly activate during the first and second bit times. ### Claim 8 A method of operation in a voltage-mode DAC, the method comprising: operating multiple bit processing circuits to generate an output voltage responsive to a binary input, the operating of each of the multiple bit processing circuits including selectively coupling one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time, the first output load having a value proportional to a scaling value d, selectively coupling one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time, the second output load having a value corresponding to the first output load; and wherein the first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to a relationship (1-d). ### Claim 9 (depends on 8) The method according to claim 8, wherein the operating is carried out using a return-to-zero protocol. ### Claim 10 (depends on 8) The method according to claim 8, wherein the selectively coupling to the first and second output loads is carried out in response to alternatingly activating corresponding first and second switch circuits. ### Claim 11 A voltage-mode driver, comprising: a first voltage-mode sub-driver to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time, the first output load having a value proportional to a scaling value d, a second voltage-mode sub-driver to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time, the second output load having a value corresponding to the first output load, and wherein the first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to a relationship (1-d). ### Claim 12 (depends on 11) The voltage-mode driver according to claim 11, wherein the first and second voltage-mode sub-drivers each comprise push-pull voltage-mode sub-drivers. ### Claim 13 (depends on 11) The voltage-mode DAC according to claim 11, wherein the scaling value d comprises a selectable value between 0 and 1 such that the first and second output loads cooperate to exhibit hybrid direct driver and split driver characteristics. ### Claim 14 (depends on 11) The voltage-mode DAC according to claim 11, wherein the first and second switching circuits are sequenced during the first and second bit times in accordance with a return-to-zero protocol. ### Claim 15 (depends on 11) The voltage-mode DAC according to claim 11, further comprising: a current-steering output stage coupled to the third output load. ### Claim 16 (depends on 15) The voltage-mode DAC according to claim 15, wherein the current-steering output stage includes tunable current source/sink circuitry to compensate for common-mode data signals. ### Claim 17 (depends on 11) The voltage-mode DAC according to claim 11, wherein the first and second switch circuits alternatingly activate during the first and second bit times.