# US 10,771,074 B1 · Low power high bandwidth high speed comparator

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- Number: US 10,771,074 B1
- Document ID: US10771074B1
- Status: Granted
- Kind: B1
- Application number: 16/283,194
- Filed: 2019-02-22
- Published: 2020-08-27
- Granted: 2020-09-08
- Earliest claimed: 2019-02-22
- Assignees: Analog Devices, Inc.
- Applicants: Analog Devices, Inc.
- Inventors: Paritosh Bhoraskar; Ahmed Mohamed Abdelatty Ali; Christopher Daniel Dillon
- Web page: https://patentgrep.com/patent/US10771074B1

## CPC

- H03M 1/002: {Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed}
- H03K 3/356139: {with synchronous operation}
- H03K 3/356191: {with synchronous operation}
- H03K 5/2481: {with at least one differential stage}
- H03K 5/249: {using clock signals}
- H03M 1/0602: {of deviations from the desired transfer characteristic (H03M1/0617 takes precedence)}
- H03M 1/0845: {of power supply variations, e.g. ripple}
- H03M 1/0872: {by disabling changes in the output during the transitions, e.g. by holding or latching}
- H03M 1/00: Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00)
- H03M 1/10: Calibration or testing
- H03M 1/12: Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence)
- H03M 1/802: {using capacitors, e.g. neuron-mos transistors, charge coupled devices}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Comparators are implemented in many circuits, including analog-to-digital converters (ADCs). Some ADCs demand high bandwidth, low power consumption, and high speed. To address these requirements, a comparator circuit can be implemented without a separate pre-amplifier, where a sampling network drives a latch directly. Specifically, the comparator circuit integrates a pre-amplifier within the latch in a manner that ensures low power and high speed operation.

## Claims

### Claim 1

A low power and high bandwidth comparator, comprising:
a sampling network to derive a difference between an input signal and a reference;
a latch comprising a first cross-coupled pair of transistors and output nodes at respective first terminals of the first cross-coupled pair of transistors, wherein gates of the first cross-coupled pair of transistors are cross-coupled to the output nodes; and
first and second transistors to couple the difference from the sampling network to the gates of the first cross-coupled pair of transistors respectively.

### Claim 2 (depends on 1)

The low power and high bandwidth comparator of claim 1, wherein the gates of the first cross-coupled pair of transistors are cross-coupled to the output nodes via respective level-shifting capacitors.

### Claim 3 (depends on 1)

The low power and high bandwidth comparator of claim 1, wherein the latch further comprises:
a second cross-coupled pair of transistors having first terminals at the respective output nodes and gates cross-coupled to the output nodes.

### Claim 4 (depends on 1)

The low power and high bandwidth comparator of claim 1, wherein the latch further comprises:
a tail current transistor coupled to second terminals of the first cross-coupled pair of transistors, wherein the tail current transistor is biased to set a current in the latch during an acquire phase of the latch.

### Claim 5 (depends on 4)

The low power and high bandwidth comparator of claim 4, wherein the latch further comprises:
a replica bias branch to bias the tail current transistor.

### Claim 6 (depends on 1)

The low power and high bandwidth comparator of claim 1, wherein the latch further comprises:
a transistor coupled to second terminals of the first cross-coupled pair of transistors, wherein the transistor is biased to turn on during a regeneration phase of the latch.

### Claim 7 (depends on 1)

The low power and high bandwidth comparator of claim 1, wherein the latch further comprises:
a latching switch coupled across the output nodes, wherein the latching switch is biased to turn on during an acquire phase of the latch and turn off during a regeneration phase of the latch.

### Claim 8 (depends on 1)

The low power and high bandwidth comparator of claim 1, wherein the latch further comprises:
a reset switch coupled across the gates of the first cross-coupled pair of transistors, wherein the reset switch is biased to turn on during a reset phase of the latch.

### Claim 9 (depends on 1)

The low power and high bandwidth comparator of claim 1, wherein the sampling network comprises switches and capacitors to sample the reference onto the capacitors, and connect the capacitors to receive the input signal and derive the difference.

### Claim 10 (depends on 1)

The low power and high bandwidth comparator of claim 1, wherein the latch further comprises:
first latching switch coupled across a first one of the output nodes and a supply; and
second latching switch coupled across a second one of the output nodes and the supply;
wherein the first and second latching switches are biased to turn on during an acquire phase of the latch and turn off during a regeneration phase of the latch.

### Claim 11

A low power and high bandwidth comparator, comprising:
a switched capacitor network to sample an input signal and derive a difference between the input signal and a reference; and
a latch having an integrated pre-amplifier, latching circuitry, and output nodes, wherein the integrated pre-amplifier and the latching circuitry share the output nodes, and the difference drives the integrated pre-amplifier during an acquire phase of the latch; wherein the integrated pre-amplifier comprises a first cross-coupled pair of transistors, and the first cross-coupled pair of transistors have gates which are cross-coupled to the output nodes via respective level-shifting capacitors.

### Claim 12 (depends on 11)

The low power and high bandwidth comparator of claim 11, wherein:
the integrated pre-amplifier comprises a tail current transistor coupled to second terminals of the first cross-coupled pair of transistors.

### Claim 13 (depends on 12)

The low power and high bandwidth comparator of claim 12, wherein:
the output nodes are at respective first terminals of the first cross-coupled pair of transistors;
the difference drives gates of the first cross-coupled pair of transistors during the acquire phase of the latch; and
the tail current transistor sets a current in the latch during the acquire phase of the latch.

### Claim 14 (depends on 11)

The low power and high bandwidth comparator of claim 11, wherein:
the latching circuitry comprises the first cross-coupled pair of transistors of a first type, a second cross-coupled pair of transistors of a second type different from the first type, and a latching switch coupled across the output nodes.

### Claim 15 (depends on 14)

The low power and high bandwidth comparator of claim 14, wherein:
the output nodes are at respective first terminals of the second cross-coupled pair of transistors, and are cross-coupled to gates of the second cross-coupled pair of transistors.

### Claim 16

A method for performing a latched comparison, comprising:
comparing an input signal against a reference to generate a difference;
acquiring and amplifying the difference driving gates of a first cross-coupled pair of transistors using the difference, and setting a current through the first cross-coupled pair of transistors using a tail current transistor connected to sources of the first cross-coupled pair of transistors; and
latching the difference by the first cross-coupled pair of transistors and second cross-coupled pair of transistors.

### Claim 17 (depends on 16)

The method of claim 16, wherein comparing the input signal against the reference comprises:
sampling the reference onto capacitors; and
connecting the capacitors to sample the input signal and derive the difference.

### Claim 18 (depends on 16)

The method of claim 16, wherein latching the difference comprises:
decoupling, using level-shifting capacitors, gate-to-source voltage of the first cross-coupled pair of transistors and gate-to-source voltage of the second cross-coupled pair of transistors.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
resetting by connecting gates of the first cross-coupled pair of transistors to a common mode voltage, and connecting drains of the first cross-coupled pair of transistors together.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
resetting by connecting gates of the first cross-coupled pair of transistors together, and connecting drains of the first cross-coupled pair of transistors together.