# US 10,771,068 B2 · Reducing chip latency at a clock boundary by reference clock phase adjustment

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- Number: US 10,771,068 B2
- Document ID: US10771068B2
- Status: Granted
- Kind: B2
- Application number: 15/899,370
- Filed: 2018-02-20
- Published: 2019-08-22
- Granted: 2020-09-08
- Earliest claimed: 2018-02-20
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Steven R. Carlough; Susan M. Eickhoff; Michael W. Harper; Michael B. Spear; Gary A. Van Huben
- Web page: https://patentgrep.com/patent/US10771068B2

## CPC

- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F 5/06: for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor (G06F7/78 takes precedence)}
- G06F 11/1604: {where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware}
- H03L 7/08: Details of the phase-locked loop
- H03L 7/081: provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)}
- H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00)
- H04L 7/0037: {Delay of clock signal}
- G06F 2205/061: Adapt frequency, i.e. clock frequency at one side is adapted to clock frequency, or average clock frequency, at the other side; Not pulse stuffing only
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A calibration controller of a receiving chip learns a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of the receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary. The calibration controller dynamically adjusts a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

## Claims

### Claim 1

A method comprising:
learning, by a computer system, a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of a receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary by:
running, by the computer system, a first test line sequence on the data path comprising a plurality of line test cycles;
observing, by the computer system, a comparison of data rising output from the buffer on a rising edge of the chip clock compared with an output of a pattern generator in comparison with an expected output;
in response to the comparison matching the expected output, decrementing, by the computer system, a load to unload delay across the clock boundary by advancing each of an unload pointer for controlling output from the buffer and the pattern generator by two chip clock cycles in one line test cycle of the plurality of line test cycles;
observing, by the computer system, the comparison of the data rising output from the buffer on the rising edge of the chip clock compared with the output of the pattern generator in comparison with the expected output;
in response to the comparison not matching the expected output, incrementing, by the computer system, the load to unload delay by freezing each of the unload pointer and the pattern generator by one chip clock cycle in the one line test cycle; and
capturing and comparing, by the computer system, the data rising output from the buffer on the rising edge of the chip clock compared with the data falling output from the buffer on the falling edge of the chip clock; and
dynamically adjusting, by the computer system, a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

### Claim 2 (depends on 1)

The method according to claim 1, wherein learning, by a computer system, a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of a receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary further comprises:
learning, by the computer system, the difference between the first clock phase of the input clock and the second phase of the chip clock on the data path of the receiving chip receiving data into the buffer from another chip across a high speed serial interface operating at a first frequency, wherein the first frequency is higher than a second frequency of the chip clock driving the chip.

### Claim 3 (depends on 1)

The method according to claim 1, further comprising:
in response to the data rising output matching the data falling output, determining, by the computer system, whether the phase locked loop drift is less than a delay number for the latency plus a half a cycle;
in response to determining the phase locked loop drift is less than a delay number for the latency plus a half a cycle, incrementing, by the computer system, the load to unload delay for triggering loading of the buffer by the input clock to triggering unloading of the buffer by the chip clock by the delay number; and
in response to determining the phase locked loop drift is not less than a delay number for the latency plus a half a cycle:
inverting, by the computer system, the phase of the reference clock;
decrementing, by the computer system, the load to unload delay by advancing each of the unload pointer and the pattern generator by two chip clock cycles in the one line test cycle;
observing, by the computer system, the comparison of the data rising output from the buffer on the rising edge of the chip clock compared with the output of the pattern generator in comparison with the expected output;
in response to the comparison not matching the expected output, incrementing, by the computer system, the load to unload delay by freezing each of the unload pointer and the pattern generator by one chip clock cycle in the one line test cycle; and
incrementing, by the computer system, the load to unload delay by the delay number.

### Claim 4 (depends on 1)

The method according to claim 1, further comprising:
in response to the data rising output not matching the data falling output, determining, by the computer system, whether the phase locked loop drift is less than a delay number for the latency plus a half a cycle;
in response to determining the phase locked loop drift is not less than a delay number for the latency plus a half a cycle, incrementing, by the computer system, the load to unload delay for triggering loading of the buffer by the input clock to triggering unloading of the buffer by the chip clock by the delay number; and
in response to determining the phase locked loop drift is less than a delay number for the latency plus a half a cycle:
inverting, by the computer system, the phase of the reference clock;
decrementing, by the computer system, the load to unload delay by advancing each of the unload pointer and the pattern generator by two chip clock cycles in the one line test cycle;
observing, by the computer system, the comparison of the data rising output from the buffer on the rising edge of the chip clock compared with the output of the pattern generator in comparison with the expected output;
in response to the comparison not matching the expected output, incrementing, by the computer system, the load to unload delay by freezing each of the unload pointer and the pattern generator by one chip clock cycle in the one line test cycle; and
incrementing, by the computer system, the load to unload delay by the delay number.

### Claim 5 (depends on 1)

The method according to claim 1, wherein dynamically adjusting, by the computer system, a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity further comprises:
dynamically adjusting, by the computer system, the second clock phase by adjusting the phase of the reference clock driving the phase locked loop that outputs the chip clock, wherein the phase locked loop comprises an external feedback loop for controlling a deterministic phase of the chip clock.

### Claim 6 (depends on 1)

The method according to claim 1, wherein dynamically adjusting, by the computer system, a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity further comprises:
dynamically adjusting, by the computer system, the phase of the reference clock by adjusting an input to an exclusive OR gate to rotate the phase of the reference clock input to the phase locked loop by 180 degrees.

### Claim 7

A computer system comprising one or more processors, one or more computer-readable memories, one or more computer-readable storage devices, and program instructions, stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, the stored program instructions comprising:
program instructions to learn a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of a receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary by:
program instructions to run a first test line sequence on the data path comprising a plurality of line test cycles;
program instructions to observe a comparison of data rising output from the buffer on a rising edge of the chip clock compared with an output of a pattern generator in comparison with an expected output;
in response to the comparison matching the expected output, program instructions to decrement a load to unload delay across the clock boundary by advancing each of an unload pointer for controlling output from the buffer and the pattern generator by two chip clock cycles in one line test cycle of the plurality of line test cycles;
program instructions to observe the comparison of the data rising output from the buffer on the rising edge of the chip clock compared with the output of the pattern generator in comparison with the expected output program instructions, in response to the comparison not matching the expected output, to increment the load to unload delay by freezing each of the unload pointer and the pattern generator by one chip clock cycle in the one line test cycle; and
program instructions to capture and compare the data rising output from the buffer on the rising edge of the chip clock compared with the data falling output from the buffer on the falling edge of the chip clock; and
program instructions to dynamically adjust a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

### Claim 8 (depends on 7)

The computer system according to claim 7, the stored program instructions further comprising:
program instructions to learn the difference between the first clock phase of the input clock and the second phase of the chip clock on the data path of the receiving chip receiving data into the buffer from another chip across a high speed serial interface operating at a first frequency, wherein the first frequency is higher than a second frequency of the chip clock driving the chip.

### Claim 9 (depends on 7)

The computer system according to claim 7, the stored program instructions further comprising:
program instructions, in response to the data rising output matching the data falling output, to determine whether the phase locked loop drift is less than a delay number for the latency plus a half a cycle;
program instructions, in response to determining the phase locked loop drift is less than a delay number for the latency plus a half a cycle, to increment the load to unload delay for triggering loading of the buffer by the input clock to triggering unloading of the buffer by the chip clock by the delay number; and
program instructions, in response to determining the phase locked loop drift is not less than a delay number for the latency plus a half a cycle to:
invert the phase of the reference clock;
decrement the load to unload delay by advancing each of the unload pointer and the pattern generator by two chip clock cycles in the one line test cycle;
observe the comparison of the data rising output from the buffer on the rising edge of the chip clock compared with the output of the pattern generator in comparison with the expected output;
in response to the comparison not matching the expected output, increment the load to unload delay by freezing each of the unload pointer and the pattern generator by one chip clock cycle in the one line test cycle; and
increment the load to unload delay by the delay number.

### Claim 10 (depends on 7)

The computer system according to claim 7, the stored program instructions further comprising:
program instructions, in response to the data rising output not matching the data falling output, to determine whether the phase locked loop drift is less than a delay number for the latency plus a half a cycle;
program instructions, in response to determining the phase locked loop drift is not less than a delay number for the latency plus a half a cycle, to increment the load to unload delay for triggering loading of the buffer by the input clock to triggering unloading of the buffer by the chip clock by the delay number; and
program instructions, in response to determining the phase locked loop drift is less than a delay number for the latency plus a half a cycle to:
invert the phase of the reference clock;
decrement the load to unload delay by advancing each of the unload pointer and the pattern generator by two chip clock cycles in the one line test cycle;
observe the comparison of the data rising output from the buffer on the rising edge of the chip clock compared with the output of the pattern generator in comparison with the expected output;
in response to the comparison not matching the expected output, increment the load to unload delay by freezing each of the unload pointer and the pattern generator by one chip clock cycle in the one line test cycle; and
increment the load to unload delay by the delay number.

### Claim 11 (depends on 7)

The computer system according to claim 7, the stored program instructions further comprising:
program instructions to dynamically adjust the second clock phase by adjusting the phase of the reference clock driving the phase locked loop that outputs the chip clock, wherein the phase locked loop comprises an external feedback loop for controlling a deterministic phase of the chip clock.

### Claim 12 (depends on 7)

The computer system according to claim 7, the stored program instructions further comprising:
program instructions to dynamically adjust the phase of the reference clock by adjusting an input to an exclusive OR gate to rotate the phase of the reference clock input to the phase locked loop by 180 degrees.

### Claim 13

A computer program product comprising one or more computer-readable storage devices and program instructions, stored on at least one of the one or more storage devices, the stored program instructions comprising:
program instructions to learn a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of a receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary by:
program instructions to run a first test line sequence on the data path comprising a plurality of line test cycles;
program instructions to observe a comparison of data rising output from the buffer on a rising edge of the chip clock compared with an output of a pattern generator in comparison with an expected output;
in response to the comparison matching the expected output, program instructions to decrement a load to unload delay across the clock boundary by advancing each of an unload pointer for controlling output from the buffer and the pattern generator by two chip clock cycles in one line test cycle of the plurality of line test cycles;
program instructions to observe the comparison of the data rising output from the buffer on the rising edge of the chip clock compared with the output of the pattern generator in comparison with the expected output;
program instructions, in response to the comparison not matching the expected output, to increment the load to unload delay by freezing each of the unload pointer and the pattern generator by one chip clock cycle in the one line test cycle; and
program instructions to capture and compare the data rising output from the buffer on the rising edge of the chip clock compared with the data falling output from the buffer on the falling edge of the chip clock; and
program instructions to dynamically adjust a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

### Claim 14 (depends on 13)

The computer program product according to claim 13, the stored program instructions further comprising:
program instructions to learn the difference between the first clock phase of the input clock and the second phase of the chip clock on the data path of the receiving chip receiving data into the buffer from another chip across a high speed serial interface operating at a first frequency, wherein the first frequency is higher than a second frequency of the chip clock driving the chip.