# US 10,771,065 B2 · Charge pump circuits for clock and data recovery > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,771,065 B2 - Document ID: US10771065B2 - Status: Granted - Kind: B2 - Application number: 16/664,666 - Filed: 2019-10-25 - Published: 2020-02-20 - Granted: 2020-09-08 - Earliest claimed: 2017-07-28 - Assignees: Inphi Corporation - Applicants: Inphi Corporation - Inventors: Simon Forey; Parmanand Mishra; Michael S. Harwood; Rajasekhar Nagulapalli - Web page: https://patentgrep.com/patent/US10771065B2 ## CPC - H03L 7/0802: {the loop being adapted for reducing power consumption (H03L7/14 takes precedence)} - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - H03K 5/135: by the use of time reference signals, e.g. clock signals - H03L 7/07: using several loops, e.g. for redundant clock signal generation - H03L 7/0807: {concerning mainly a recovery circuit for the reference signal} - H03L 7/0814: {the phase shifting device being digitally controlled} - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03L 7/0995: {the oscillator comprising a ring oscillator} - H03L 7/187: using means for coarse tuning the voltage controlled oscillator of the loop (H03L7/191 - H03L7/195 take precedence) - H04L 7/0058: {detection of error based on equalizer tap values} - H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well. ## Claims ### Claim 1 A charge pump device comprising: a first switch comprises a first output and coupled to a late signal; a second switch comprises a second output and coupled to an early signal, the second output being directly coupled to the first output; an output resistor coupled to the first output and the second output and configured to output a charge pump current based at least on the first output and the second output; and a first resistor coupled to the first switch; a second resistor coupled to the second switch; wherein the charge pump current is at a high voltage when the first switch is on. ### Claim 2 (depends on 1) The device of claim 1 further comprising a third switch for providing equalization between the first switch and the second switch. ### Claim 3 (depends on 1) The device of claim 1 wherein the charge pump current is low when the second switch is on. ### Claim 4 (depends on 1) The device of claim 1 further comprises an operational amplifier coupled to the second switch via a first resistor. ### Claim 5 (depends on 1) The device of claim 1 wherein the charge pump current has a magnitude of less than 40 uA. ### Claim 6 (depends on 1) The device of claim 1 wherein the first switch is coupled to a first capacitor, and the second switch is coupled to a second capacitor, the first capacitor and the second capacitor are a matched pair. ### Claim 7 (depends on 1) The device of claim 1 wherein the first resistor and the second resistor are a matched pair. ### Claim 8 (depends on 1) The device of claim 1 further comprising an input transistor coupled to a digital-to-analog converter. ### Claim 9 (depends on 1) The device of claim 1 wherein the charge pump current is positive when the first switch is closed. ### Claim 10 (depends on 1) The device of claim 1 wherein the charge pump current is negative when the first switch is closed. ### Claim 11 A clock data recover (CDR) device configured to generate a clock signal based on an input data stream, the device comprising: a data sampler for sampling the input data stream; a phase detector configured to generate an early signal and a late signal based on the input data stream; a charge pump comprising a first switch and a second switch and a third switch, the first switch being coupled to a first differential voltage based on the late signal, the second switch being coupled to a second differential voltage based on the early signal, the charge pump being configured to generate an offset signal for adjusting the clock signal using a charge pump current based on the first differential voltage and the second differential voltage, the third switch being configured to provide equalization between the first switch and the second switch; a loop filter; and a voltage-controlled oscillator (VCO). ### Claim 12 (depends on 11) The device of claim 11 further comprising an edge sampler. ### Claim 13 (depends on 11) The device of claim 11 wherein phase detector comprises a bang-bang phase detector. ### Claim 14 (depends on 11) The device of claim 11 wherein the data sampler is coupled to an amplifier. ### Claim 15 (depends on 11) The device of claim 11 wherein the loop filter is configured to generate a loop filter voltage. ### Claim 16 (depends on 11) The device of claim 11 further comprising an output terminal coupled to a de-multiplexer. ### Claim 17 A charge pump circuit device comprising: a first transistor configured to generate a first differential voltage based on an input signal, the first transistor comprising a first gate terminal and a first output terminal; a first resistor and a second resistor coupled to a first output terminal; an operational amplifier comprising a first input terminal and a second output terminal, the second output terminal being coupled to the first output terminal; a first switch coupled to the first output terminal, the first switch being turned on by a late signal; a second transistor comprising a second gate terminal and a third output terminal, the second gate terminal being coupled to the second output terminal; a third resistor coupled to the third output terminal; a second switch coupled to the third output terminal, the second switch being turned on by an early signal; and a fourth resistor coupled to the first switch and the second switch, the fourth resistor being associated with a charge pump current, the charge pump current being at a high voltage when the first switch is on. ### Claim 18 (depends on 17) The device of claim 17 wherein: the fourth resistor is coupled to a loop filter; the operational amplifier further comprises a fourth output signal, the fourth output signal being coupled to the loop filter. ### Claim 19 (depends on 17) The device of claim 17 further comprising a third switch coupled directly to the first switch and the second switch, the third switch being configured to provide equalization between the first switch and the second switch. ### Claim 20 (depends on 17) The device of claim 17 wherein the second resistor and the third resistor are a matched pair.