# US 10,771,062 B1 · Systems and methods for enhancing confidentiality via logic gate encryption

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- Number: US 10,771,062 B1
- Document ID: US10771062B1
- Status: Granted
- Kind: B1
- Application number: 16/100,130
- Filed: 2018-08-09
- Granted: 2020-09-08
- Earliest claimed: 2014-10-01
- Assignees: Maxim Integrated Products, Inc.
- Applicants: Maxim Integrated Products, Inc.
- Inventors: Robert Michael Muchsel; Donald Wood Loomis, III; Edward Tangkwai Ma; Hung Thanh Nguyen; Nancy Kow Iida; Mark Alan Lovell
- Web page: https://patentgrep.com/patent/US10771062B1

## CPC

- H03K 19/00315: {in field-effect transistor circuits}
- H04L 9/0861: {Generation of secret information including derivation or calculation of cryptographic keys or passwords}
- H04L 9/0866: {involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics}
- H04L 2209/24: Key scheduling, i.e. generating round keys or sub-keys for block encryption
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Presented are systems and methods that allow hardware designers to protect valuable IP and information in the hardware domain in order to increase overall system security. In various embodiments of the invention this is accomplished by configuring logic gates of existing logic circuitry based on a key input. In certain embodiments, a logic function provides results that are dependent not only on input values but also on an encrypted logic key that determines connections for a given logic building block, such that the functionality of the logic function cannot be determined by reverse engineering. In some embodiments, the logic key is created by decrypting a piece of data using a secret or private key. Advantages of automatic encryption include that existing circuitry need not be re-implemented or re-built, and that the systems and methods presented are backward compatible with standard manufacturing tools.

## Claims

### Claim 1

A configurable logic cell to increase confidentiality via logic gate encryption, the logic cell comprising:
a reconfigurable circuit comprising one or more reconfigurable logic building blocks that comprise logic gates, the reconfigurable circuit is configured to perform functions equivalent to a non-reconfigurable circuit that has been assigned key bits.

### Claim 2 (depends on 1)

The configurable logic cell according to claim 1, wherein the reconfigurable logic building blocks are indistinguishable from each other.

### Claim 3 (depends on 1)

The configurable logic cell according to claim 1, wherein the key bits have been serialized into a known sequence of the non-reconfigurable circuit.

### Claim 4 (depends on 1)

The configurable logic cell according to claim 1, wherein the one or more reconfigurable logic building blocks comprise a universal logic gate.

### Claim 5 (depends on 1)

The configurable logic cell according to claim 1, wherein key bits are stored in a tamperproof storage element.

### Claim 6 (depends on 5)

The configurable logic cell according to claim 5, wherein a concatenation of the key bits yields an unlocking key.

### Claim 7 (depends on 6)

The configurable logic cell according to claim 6, wherein the unlocking key has been pre-computed based on a non-secure physical element and one of a secret and a private key.

### Claim 8 (depends on 1)

The configurable logic cell according to claim 1, wherein the reconfigurable logic building blocks are configured to record the key bits such that the sequence of the key bits corresponds to the sequence of logic gates.

### Claim 9 (depends on 1)

The configurable logic cell according to claim 1, further comprising a predetermined number of inverting elements at inputs of reconfigurable logic blocks.

### Claim 10

A method to increase confidentiality via logic gate encryption, the method comprising:
assigning key bits to logic gates; and
replacing one or more logic gates of a non-reconfigurable circuit with reconfigurable logic building blocks, such that the reconfigurable logic building blocks perform functions equivalent to the non-reconfigurable circuit according to the key bits.

### Claim 11 (depends on 10)

The method according to claim 10, wherein a sequence of logic gates has been obtained by serializing the one or more logic gates.

### Claim 12 (depends on 10)

The method according to claim 10, associating a sequence of key bits with a mathematical function whose inverse provides a value for an unlocking key.

### Claim 13 (depends on 12)

The method according to claim 12, further comprising recording the key bits into the reconfigurable logic building blocks such that the sequence of key bits corresponds to a sequence of logic gates.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the sequence of logic gates represents a logic function.

### Claim 15 (depends on 12)

The method according to claim 12, further comprising performing a self-test when loading of the sequence of key bits into the reconfigurable logic building blocks to configure the reconfigurable logic building blocks.

### Claim 16 (depends on 10)

The method according to claim 10, further comprising generating a decrypted logic key from an encrypted logic key and a decryption key.

### Claim 17 (depends on 16)

The method according to claim 16, wherein the decrypted logic key and the decryption key have a different length.

### Claim 18 (depends on 10)

The method according to claim 10, further comprising performing a software bit inversion that generates an inverted output.

### Claim 19 (depends on 10)

The method according to claim 10, further comprising storing the key bits in a device-unique secure physical element.

### Claim 20 (depends on 16)

The method according to claim 16, further comprising using the encrypted logic key to determine physical connections for a logic building block to encrypt the logic building block.