# US 10,771,057 B1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,771,057 B1 - Document ID: US10771057B1 - Status: Granted - Kind: B1 - Application number: 16/745,456 - Filed: 2020-01-17 - Granted: 2020-09-08 - Earliest claimed: 2019-09-17 - Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation - Applicants: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation - Inventors: Akira Yoshioka; Toru Sugiyama; Masaaki Iwai; Naonori Hosokawa; Masaaki Onomura; Hung Hung; Yasuhiro Isobe - Web page: https://patentgrep.com/patent/US10771057B1 ## CPC - H02M 7/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections} - H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor} - H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters - H02M 7/5387: in a bridge configuration - H03K 17/04123: {in field-effect transistor switches} - H03K 17/063: {in field-effect transistor switches} - H03K 17/102: {in field-effect transistor switches} - H03K 17/161: {in field-effect transistor switches} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 90/811: {Multiple chips on leadframes} - H02P 27/06: using DC to AC converters or inverters (H02P27/05 takes precedence) - H03K 2017/6875: {using self-conductive, depletion FETs} - H10W 72/07554: {changes in dispositions} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/5473: {multiple bond wires connected to a common bond pad} - H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 90/00: Package configurations - H10W 90/753: {between laterally-adjacent chips} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H02P: CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS ## Abstract A semiconductor device of embodiments includes a first normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode via a first wiring, a fourth electrode, and a second control electrode, a second normally-off transistor having a fifth electrode, a sixth electrode electrically connected to the third electrode via a second wiring, and a third control electrode, a first diode having a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and a capacitor having a first end portion connected to the first anode and the second control electrode and a second end portion. ## Claims ### Claim 1 A semiconductor device comprising: a first normally-off transistor having a first electrode, a second electrode, and a first control electrode; a normally-on transistor having a third electrode electrically connected to the second electrode via a first wiring, a fourth electrode, and a second control electrode; a second normally-off transistor having a fifth electrode, a sixth electrode electrically connected to the third electrode via a second wiring, and a third control electrode; a first diode having a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode; and a capacitor having a first end portion connected to the first anode and the second control electrode and a second end portion. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein, when an on-resistance of the first normally-off transistor is denoted by Ron1, an on-resistance of the second normally-off transistor is denoted by Ron2, an inductance of the first wiring is denoted by Ls1, and an inductance of the second wiring is denoted by Ls2, (Ron2×Ls1)/(Ron1×Ls2)>2. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein Ron1