# US 10,771,053 B2 · Semiconductor device having first and second switching regions respectively controlled by first and second control signals output by a controller

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- Number: US 10,771,053 B2
- Document ID: US10771053B2
- Status: Granted
- Kind: B2
- Application number: 16/415,643
- Filed: 2019-05-17
- Published: 2020-03-12
- Granted: 2020-09-08
- Earliest claimed: 2018-09-10
- Assignees: Mitsubishi Electric Corporation
- Applicants: Mitsubishi Electric Corporation
- Inventors: Keisuke Eguchi; Takahiro Inoue; Rei Yoneyama; Shiori Uota; Haruhiko Murakami
- Web page: https://patentgrep.com/patent/US10771053B2

## CPC

- H03K 17/567: Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
- H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor}
- H10W 90/00: Package configurations
- H02M 1/088: for the simultaneous control of series or parallel connected semiconductor devices
- H10W 72/07554: {changes in dispositions}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

First and second switching regions include first and second gate electrodes respectively. Channel currents of the first and second switching regions are controlled according to electric charge amounts supplied by control signals input to the first and second gate electrodes respectively. The second switching region is connected in parallel with the first switching region. A control section outputs a first control signal for turning-on the first switching region to the first gate electrode and a second control signal for turning-on the second switching region to the second gate electrode. The control section stops outputting the second control signal after a first predetermined period elapses from a start of outputting the first and second control signals, and outputs the second control signal after a second predetermined period elapses from a stop of outputting the second control signal.

## Claims

### Claim 1

A semiconductor device comprising:
a first switching region including a first gate electrode wherein a channel current of the first switching region is controlled according to an electric charge amount supplied by a first control signal input to the first gate electrode;
a second switching region including a second gate electrode and connected in parallel with the first switching region wherein a channel current of the second switching region is controlled according to an electric charge amount supplied by a second control signal input to the second gate electrode; and
a control section outputting the first control signal for turning-on the first switching region to the first gate electrode and the second control signal for turning-on the second switching region to the second gate electrode,
wherein the control section stops outputting the second control signal after a first predetermined period elapses from a start of outputting the first and second control signals, and outputs the second control signal after a second predetermined period elapses from a stop of outputting the second control signal.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein a voltage of the second gate electrode at a time when the second predetermined period elapses is lower than a voltage of the second gate electrode at a time when the first predetermined period elapses.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the first switching region and the second switching region are provided on one semiconductor substrate.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the first switching region and the second switching region are provided on different semiconductor substrates respectively.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, comprising a voltage detection circuit detecting a voltage between a high-potential side electrode and a low-potential side electrode,
wherein the first switching region or the second switching region is electrically connected to the high-potential side electrode and the low-potential side electrode, and
the control section controls the second predetermined period based on the voltage between the high-potential side electrode and the low-potential side electrode detected by the voltage detection circuit.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein when a voltage between the high-potential side electrode and the low-potential side electrode detected by the voltage detection circuit during the second predetermined period is smaller than a predetermined threshold which is smaller than a voltage between the high-potential side electrode and the low-potential side electrode detected by the voltage detection circuit at the start of the first predetermined period, the control section outputs the second control signal.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the threshold is less than 10% of the voltage between the high-potential side electrode and the low-potential side electrode detected by the voltage detection circuit at the start of the first predetermined period.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the electric charge amount supplied to the second gate electrode is larger than the electric charge amount supplied to the first gate electrode.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein capacitance of the second gate electrode is larger than capacitance of the first gate electrode.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein the number of the second gate electrodes is larger than the number of the first gate electrodes.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the first switching region and the second switching region are provided in a wide-bandgap semiconductor having a bandgap wider than that of silicon.