# US 10,771,049 B1 · Control circuit and method for avoiding reverse recovery of a power transistor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,771,049 B1 - Document ID: US10771049B1 - Status: Granted - Kind: B1 - Application number: 16/456,233 - Filed: 2019-06-28 - Granted: 2020-09-08 - Earliest claimed: 2019-06-28 - Assignees: Dialog Semiconductor (UK) Limited - Applicants: Dialog Semiconductor (UK) Limited - Inventors: Ambreesh Bhattad; Horst Knoedgen - Web page: https://patentgrep.com/patent/US10771049B1 ## CPC - H03K 17/04206: {in field-effect transistor switches} - H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters - H03K 17/04123: {in field-effect transistor switches} - H03K 17/133: {in field-effect transistor switches} - H03K 17/145: {in field-effect transistor switches} - H03K 17/162: {without feedback from the output circuit to the control circuit} - H02M 1/0054: {Transistor switching losses (periodically suspending operation of switching converter in low power mode H02M1/0035)} - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract The present document describes a control circuit and a method for controlling a power transistor, wherein the power transistor has a drain, a gate and a source. The power transistor has a body diode. The control circuit is configured to predict a time instant at which a drain potential at the drain falls below a source potential at the source of the power transistor by more than a diode threshold voltage of the body diode. Furthermore, the control circuit is configured to apply a pre-bias potential and/or provide a pre-bias current to the gate of the power transistor in dependence the predicted time instant, such that a conducting channel between the drain and the source is provided, which at least partially takes over current which would otherwise flow through the body diode. ## Claims ### Claim 1 A control circuit for controlling a power transistor; wherein the power transistor exhibits a drain, a gate and a source, and wherein the power transistor exhibits a body diode; wherein the control circuit is configured to predict a time instant at which a drain potential at the drain falls below a source potential at the source of the power transistor by more than a diode threshold voltage of the body diode; and apply a pre-bias potential and/or provide a pre-bias current to the gate of the power transistor in dependence of the predicted time instant, such that a conducting channel between the drain and the source is provided, which at least partially takes over current which would otherwise flow through the body diode. ### Claim 2 (depends on 1) The control circuit of claim 1, wherein the power transistor is repeatedly turned on and off at turn-on time instants and at turn-off time instants, respectively; and the predicted time instant directly precedes a turn-on time instant or a turn-off time instant. ### Claim 3 (depends on 1) The control circuit of claim 1, wherein the power transistor is part of a half bridge comprising a second power transistor; the control circuit is configured to turn on the power transistor and the second power transistor repeatedly and alternately in a mutually exclusive manner, such that a time instant at which one of the power transistors of the half bridge is turned off and a subsequent time instant at which the other one of the power transistors of the half bridge is turned on are separated by a dead time interval; and the predicted time instant falls within a dead time interval. ### Claim 4 (depends on 1) The control circuit of claim 1, wherein the power transistor is a low side transistor of a half bridge which also comprises a high side transistor; the half bridge is arranged between a supply potential and a reference potential; the predicted time instant lies between a time instant at which the high side transistor is turned off and a subsequent time instant at which the power transistor is turned on; or the predicted time instant lies between a time instant at which the power transistor is turned off and a subsequent time instant at which the high side transistor is turned on. ### Claim 5 (depends on 1) The control circuit of claim 1, wherein the power transistor exhibits a threshold voltage corresponding to a minimum gate-source voltage which is to be applied to the gate of the power transistor for turning on the power transistor; and the control circuit is configured to set the pre-bias potential at a level which lies below the threshold voltage; and/or charge a gate capacitance of the power transistor using the pre-bias current such that the gate exhibits a potential which lies below the threshold voltage. ### Claim 6 (depends on 1) The control circuit of claim 1, wherein the control circuit is configured to set the pre-bias potential and/or charge a gate capacitance of the power transistor using the pre-bias current such that conduction through the body diode is prevented at the predicted time instant. ### Claim 7 (depends on 1) The control circuit of claim 1, wherein the control circuit comprises a first control switch configured to couple the gate of the power transistor with a first potential for turning on the power transistor; a second control switch configured to couple the gate of the power transistor with a second potential for turning off the power transistor; and a third control switch configured to couple the gate of the power transistor with the pre-bias potential; wherein the pre-bias potential is an intermediate potential between the first potential and the second potential. ### Claim 8 (depends on 1) The control circuit of claim 1, wherein the control circuit comprises pre-bias circuitry configured to charge a gate capacitor at the gate of the power transistor to the pre-bias potential; the pre-bias circuitry comprises an operational amplifier having an output controlling a first transistor and a second transistor; a source of the first transistor is fed back to an input of the operational amplifier; another input of the operational amplifier is coupled to a target level of the pre-bias potential; and a source of the second transistor is configured to charge the gate capacitor at the gate of the power transistor to the pre-bias potential. ### Claim 9 (depends on 1) The control circuit of claim 1, wherein the control circuit is configured to determine temperature information regarding a temperature of the power transistor; and adapt a level of the pre-bias potential and/or of the pre-bias current in dependence of the temperature information. ### Claim 10 (depends on 9) The control circuit of claim 9, wherein the control circuit is configured to increase the level of the pre-bias potential and/or of the pre-bias current, if the temperature information indicates that the temperature of the power transistor has dropped; and/or decrease the level of the pre-bias potential and/or of the pre-bias current, if the temperature information indicates that the temperature of the power transistor has increased. ### Claim 11 (depends on 1) The control circuit of claim 1, wherein the control circuit is configured to determine a voltage indication indicating a level of the drain potential at the drain of the power transistor; and adapt a level of the pre-bias potential and/or of the pre-bias current in dependence of the voltage indication. ### Claim 12 (depends on 11) The control circuit of claim 11, wherein the control circuit is configured to increase the level of the pre-bias potential and/or of the pre-bias current, if the voltage indication indicates that the drain potential has dropped further below the source potential; and/or decrease the level of the pre-bias potential and/or of the pre-bias current, if the voltage indication indicates that the drain potential has moved closer to the source potential. ### Claim 13 (depends on 1) The control circuit of claim 1, wherein the control circuit is configured to determine a load indication indicating a level of a drain-source current flowing through the power transistor, when the power transistor is turned on; and adapt a level of the pre-bias potential and/or of the pre-bias current in dependence of the load indication. ### Claim 14 (depends on 13) The control circuit of claim 13, wherein the control circuit is configured to increase the level of the pre-bias potential and/or of the pre-bias current, if the load indication indicates that the level of the drain-source current has increased; and/or decrease the level of the pre-bias potential and/or of the pre-bias current, if the load indication indicates that the level of the drain-source current has decreased. ### Claim 15 (depends on 1) The control circuit of claim 1, wherein the power transistor is operated within a host circuit, notably a power converter; and the control circuit is configured to determine an operational condition of the host circuit; and to adapt a level of the pre-bias potential and/or of the pre-bias current in dependence of the operational condition. ### Claim 16 (depends on 1) The control circuit of claim 1, wherein the control circuit is configured to determine a level of the pre-bias current in dependence of a gate capacitance of the gate of the power transistor and in dependence of a level of the pre-bias potential; and provide the determined level of the pre-bias current to the gate of the power transistor prior to the predicted time instant, such that at the predicted time instant the gate exhibits the pre-bias potential. ### Claim 17 (depends on 1) The control circuit of claim 1, wherein the power transistor is operated within a host circuit, notably a power converter; the host circuit comprises a plurality of power transistors which are operated in a corresponding plurality of parallel slices; and the control circuit is configured to determine a load indication indicating a level of a drain-source current flowing through the plurality of power transistors, when the plurality of power transistors is turned on; and adapt a number of power transistors from the plurality of power transistors, to which the pre-bias potential is applied and/or to which the pre-bias current is provided in dependence of the load indication. ### Claim 18 A method for controlling a power transistor; wherein the power transistor exhibits a drain, a gate and a source, and wherein the power transistor exhibits a body diode; wherein the method comprises predicting a time instant or time interval, at which a drain potential at the drain falls below a source potential at the source of the power transistor by more than a diode threshold voltage of the body diode; applying a pre-bias potential and/or provide a pre-bias current to the gate of the power transistor in dependence of the predicted time instant or time interval, such that a conducting channel between the drain and the source is provided, which at least partially takes over current which would otherwise flow through the body diode.