# US 10,771,045 B1 · Apparatus and method for reducing output skew and transition delay of level shifter

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- Number: US 10,771,045 B1
- Document ID: US10771045B1
- Status: Granted
- Kind: B1
- Application number: 16/451,898
- Filed: 2019-06-25
- Published: 2020-10-01
- Granted: 2020-09-08
- Earliest claimed: 2019-03-28
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Chih-Wei Chen
- Web page: https://patentgrep.com/patent/US10771045B1

## CPC

- H03K 3/356017: {using additional transistors in the input circuit (H03K3/356104, H03K3/3562 take precedence)}
- H03K 3/356104: {using complementary field-effect transistors (H03K3/35625 takes precedence)}
- H03K 3/011: Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)}
- H03K 3/012: Modifications of generator to improve response time or to decrease power consumption
- H03K 19/0185: using field effect transistors only
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An apparatus and method are provided. According to one embodiment, an apparatus includes a level-shifter circuit configured to output voltages Vo1+ and Vo1−; and an output alignment circuit configured to output voltages Vo+ and Vo− that are triggered by an edge of a combination of Vo1+ and Vo1−, and where Vo+ and Vo− are set by high states of Vo1+ and Vo1− prior to a transition on an input of the level-shifter circuit, and the method includes outputting, by a level-shifter circuit, voltages Vo1+ and Vo1−; and outputting, by an output alignment circuit, voltages Vo+ and Vo− that are triggered by an edge of a combination of Vo1+ and Vo1−, and where Vo+ and Vo− are set by high states of Vo1+ and Vo1− prior to a transition on an input of the level-shifter circuit.

## Claims

### Claim 1

An apparatus, comprising:
a level-shifter circuit configured to output voltages Vo1+ and Vo1−; and
an output alignment circuit configured to output voltages Vo+ and Vo− that are triggered by an edge of a combination of Vo1+ and Vo1−, and where Vo+ and Vo− are set by high states of Vo1+ and Vo1− prior to a transition on an input of the level-shifter circuit.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the output alignment circuit comprises:
a first inverter configured to receive a first input signal;
a second inverter configured to receive a second input signal, wherein the second input signal is an inverse of the first input signal;
a third inverter connected to the first inverter;
a fourth inverter connected to the second inverter;
a logic circuit connected to the first inverter, the second inverter, the third inverter, and the fourth inverter; and
a flip-flop connected to the logic circuit.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the logic circuit comprises:
a first NAND gate connected to the first inverter and the third inverter;
a second NAND gate connected to the second inverter and the fourth inverter;
a third NAND gate connected to the second inverter and the first NAND gate; and
a fourth NAND gate connected to the first inverter and the second NAND gate.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the level-shifter circuit is a low-to-high voltage shifter circuit.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the low-to-high voltage shifter circuit comprises:
a fifth inverter configured to receive a third input signal and including a power supply input connected to a first power supply voltage VDD1 and a ground input connected to a second power supply voltage VSS1;
a first n-channel transistor including a source connected to the second power supply voltage VSS1, a gate connected to an output of the fifth inverter, and a drain;
a second n-channel transistor including a source connected to the second power supply voltage VSS1, a gate connected to an input of the fifth inverter, and a drain;
a first p-channel transistor including a drain connected to the drain of the first n-channel transistor, a gate connected to a third power supply voltage VSS2, and a source;
a second p-channel transistor including a drain connected to the drain of the second n-channel transistor, a gate connected to the third power supply voltage VSS2, and a source;
a third p-channel transistor including a drain connected to the source of the first p-channel transistor, a gate, and a source connected to a fourth power supply voltage VDD2;
a fourth p-channel transistor including a drain connected to the source of the second p-channel transistor and the gate of the third p-channel transistor, a gate connected to the drain of the third p-channel transistor, and a source connected to the fourth power supply voltage VDD2;
a first buffer connected between the drain of the fourth p-channel transistor and the second inverter, and including a power supply input connected to the fourth power supply voltage VDD2 and a ground input connected to the third power supply voltage VSS2; and
a second buffer connected between the source of the first p-channel transistor and the first inverter, and including a power supply input connected to the fourth power supply voltage VDD2 and a ground input connected to the third power supply voltage VSS2.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein:
the first n-channel transistor and the second n-channel transistor are each an n-channel laterally diffused metal-oxide semiconductor field-effect transistor (NLDMOS);
the first p-channel transistor and the second p-channel transistor are each a p-channel laterally diffused metal-oxide semiconductor field-effect transistor (PLDMOS); and
the third p-channel transistor and the fourth p-channel transistor are each a p-channel metal oxide semiconductor field-effect transistor (PMOS).

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein VSS1 is 0 volts, VDD1 is 6 volts, VSS2 is 17 volts, and VDD2 is 23 volts.

### Claim 8 (depends on 2)

The apparatus of claim 2, wherein the level-shifter circuit is a high-to-low voltage shifter circuit.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the high-to-low voltage shifter circuit comprises:
a sixth inverter configured to receive a fourth input signal and including a power supply input connected to a fourth power supply voltage VDD2 and a ground input connected to a third power supply voltage VSS2;
a fifth p-channel transistor including a source connected to the fourth power supply voltage VDD2, a gate connected to an output of the sixth inverter, and a drain;
a sixth p-channel transistor including a source connected to the fourth power supply voltage VDD2, a gate connected to an input of the sixth inverter, and a drain;
a third n-channel transistor including a drain connected to the drain of the fifth p-channel transistor, a gate connected to a first power supply voltage VDD1, and a source;
a fourth n-channel transistor including a drain connected to the drain of the sixth p-channel transistor, a gate connected to the first power supply voltage VDD1, and a source;
a fifth n-channel transistor including a drain connected to the source of the third n-channel transistor, a gate, and a source connected to a second power supply voltage VSS1;
a sixth p-channel transistor including a drain connected to the source of the fourth n -channel transistor and the gate of the fifth n-channel transistor, a gate connected to the drain of the fifth n-channel transistor, and a source connected to the second power supply voltage VSS1;
a seventh inverter connected between the source of the third n-channel transistor and the second inverter, and including a power supply input connected to the first power supply voltage VDD1 and a ground input connected to the second power supply voltage VSS1; and
an eighth inverter connected between the drain of the sixth n-channel transistor and the first inverter, and including a power supply input connected to the first power supply voltage VDD1 and a ground input connected to the second power supply voltage VSS1.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein:
the fifth p-channel transistor and the sixth p-channel transistor are each a p-channel laterally diffused metal-oxide semiconductor field-effect transistor (PLDMOS);
the third n-channel transistor and the fourth n-channel transistor are each an n-channel laterally diffused metal-oxide semiconductor field-effect transistor (NLDMOS); and
the fifth n-channel transistor and the sixth n-channel transistor are each an n-channel metal oxide semiconductor field-effect transistor (NMOS), and wherein VSS1 is 0 volts, VDD1 is 6 volts, VSS2 is 17 volts, and VDD2 is 23 volts.

### Claim 11

A method, comprising outputting, by a level-shifter circuit, voltages Vo1+ and Vo1−, and outputting, by an output alignment circuit, voltages Vo+ and Vo− that are triggered by an edge of a combination of Vo1+ and Vo1−, and where Vo+ and Vo− are set by high states of Vo1+ and Vo1− prior to a transition on an input of the level-shifter circuit.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
inverting, by a first inverter, a first input signal;
inverting, by a second inverter, a second input signal, wherein the second input signal is an inverse of the first input signal;
inverting, by a third inverter, an output of the first inverter;
inverting, by a fourth inverter, an output of the second inverter;
reducing output skew and transition delay between the first input signal and the second input signal by a logic circuit connected to the first inverter, the second inverter, the third inverter, and the fourth inverter; and
latching the reduced output skew and transition delay between the first input signal and the second input signal by a flip-flop connected to the logic circuit.

### Claim 13 (depends on 12)

The method of claim 12, wherein the logic circuit comprises:
a first NAND gate connected to the first inverter and the third inverter;
a second NAND gate connected to the second inverter and the fourth inverter;
a third NAND gate connected to the second inverter and the first NAND gate; and
a fourth NAND gate connected to the first inverter and the second NAND gate.

### Claim 14 (depends on 12)

The method of claim 12, further comprising shifting a voltage by a low-to-high voltage shifter circuit.

### Claim 15 (depends on 14)

The method of claim 14, wherein the low-to-high voltage shifter circuit comprises:
a fifth inverter configured to receive a third input signal and including a power supply input connected to a first power supply voltage VDD1 and a ground input connected to a second power supply voltage VSSl;
a first n-channel transistor including a source connected to the second power supply voltage VSS1, a gate connected to an output of the fifth inverter, and a drain;
a second n-channel transistor including a source connected to the second power supply voltage VSS1, a gate connected to an input of the fifth inverter, and a drain;
a first p-channel transistor including a drain connected to the drain of the first n-channel transistor, a gate connected to a third power supply voltage VSS2, and a source;
a second p-channel transistor including a drain connected to the drain of the second n-channel transistor, a gate connected to the third power supply voltage VSS2, and a source;
a third p-channel transistor including a drain connected to the source of the first p-channel transistor, a gate, and a source connected to a fourth power supply voltage VDD2;
a fourth p-channel transistor including a drain connected to the source of the second -channel transistor and the gate of the third p-channel transistor, a gate connected to the drain of the third p-channel transistor, and a source connected to the fourth power supply voltage VDD2;
a first buffer connected between the drain of the fourth p-channel transistor and the second inverter, and including a power supply input connected to the fourth power supply voltage VDD2 and a ground input connected to the third power supply voltage VSS2; and
a second buffer connected between the source of the first p-channel transistor and the first inverter, and including a power supply input connected to the fourth power supply voltage VDD2 and a ground input connected to the third power supply voltage VSS2.

### Claim 16 (depends on 15)

The method of claim 15, wherein:
the first n-channel transistor and the second n-channel transistor are each an n-channel laterally diffused metal-oxide semiconductor field-effect transistor (NLDMOS);
the first p-channel transistor and the second p-channel transistor are each a p-channel laterally diffused metal-oxide semiconductor field-effect transistor (PLDMOS); and
the third p-channel transistor and the fourth p-channel transistor are each a p-channel metal oxide semiconductor field-effect transistor (PMOS).

### Claim 17 (depends on 15)

The method of claim 15, wherein VSS1 is 0 volts, VDD1 is 6 volts, VSS2 is 17 volts, and VDD2 is 23 volts.

### Claim 18 (depends on 12)

The method of claim 12, further comprising shifting a voltage by a high-to-low voltage shifter circuit.

### Claim 19 (depends on 18)

The method of claim 18, wherein the high-to-low voltage shifter circuit comprises:
a sixth inverter configured to receive a fourth input signal and including a power supply input connected to a fourth power supply voltage VDD2 and a ground input connected to a third power supply voltage VSS2;
a fifth p-channel transistor including a source connected to the fourth power supply voltage VDD2, a gate connected to an output of the sixth inverter, and a drain;
a sixth p-channel transistor including a source connected to the fourth power supply voltage VDD2, a gate connected to an input of the sixth inverter, and a drain;
a third n-channel transistor including a drain connected to the drain of the fifth p-channel transistor, a gate connected to a first power supply voltage VDD1, and a source;
a fourth n-channel transistor including a drain connected to the drain of the sixth p-channel transistor, a gate connected to the first power supply voltage VDD1, and a source;
a fifth n-channel transistor including a drain connected to the source of the third n-channel transistor, a gate, and a source connected to a second power supply voltage VSS1;
a sixth p-channel transistor including a drain connected to the source of the fourth n-channel transistor and the gate of the fifth n-channel transistor, a gate connected to the drain of the fifth n-channel transistor, and a source connected to the second power supply voltage VSS1;
a seventh inverter connected between the source of the third n-channel transistor and the second inverter, and including a power supply input connected to the first power supply voltage VDD1 and a ground input connected to the second power supply voltage VSS1; and an eighth inverter connected between the drain of the sixth n-channel transistor and the first inverter, and including a power supply input connected to the first power supply voltage VDD1 and a ground input connected to the second power supply voltage VSS1.

### Claim 20 (depends on 19)

The method of claim 19, wherein:
the fifth p-channel transistor and the sixth p-channel transistor are each a p-channel laterally diffused metal-oxide semiconductor field-effect transistor (PLDMOS);
the third n-channel transistor and the fourth n-channel transistor are each an n-channel laterally diffused metal-oxide semiconductor field-effect transistor (NLDMOS); and
the fifth n-channel transistor and the sixth n-channel transistor are each an n-channel metal oxide semiconductor field-effect transistor (NMOS), and wherein VSS1 is 0 volts, VDD1 is 6 volts, VSS2 is 17 volts, and VDD2 is 23 volts.