# US 10,771,044 B2 · On-chip emulation of large resistors for integrating low frequency filters

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- Number: US 10,771,044 B2
- Document ID: US10771044B2
- Status: Granted
- Kind: B2
- Application number: 15/250,760
- Filed: 2016-08-29
- Published: 2017-03-02
- Granted: 2020-09-08
- Earliest claimed: 2015-08-28
- Assignees: Vidatronic, Inc.
- Applicants: Vidatronic Inc.
- Inventors: Anand Veeravalli Raghupathy
- Web page: https://patentgrep.com/patent/US10771044B2

## CPC

- H03H 19/004: {Switched capacitor networks}
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03F 2200/261: Amplifier which being suitable for instrumentation applications
- H03F 2203/45528: the FBC comprising one or more passive resistors and being coupled between the LC and the IC
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)
- H03F: AMPLIFIERS

## Abstract

A system for processing of signals with poles that are low in frequency includes a switched capacitor circuit that includes two switches connected to an input and an output of a switching capacitor (Cs), respectively, in an alternating manner at a selected switching frequency (fSW); and a filter capacitor connected between an input and the switched capacitor circuit. The filter capacitor and the switched capacitor circuit together function as a filter, thereby a pole frequency depending on a ratio of capacitance of the switching capacitor (Cs) and the filter capacitor, instead of an RC product.

## Claims

### Claim 1

A system for processing of signals with poles that are low in frequency, comprising:
a switching capacitor circuit network comprising two switches connected to an input and an output of a switching capacitor (Cs), respectively, in an alternating manner at a selected frequency (fSW), wherein the switching capacitor circuit network is connected to a common mode reference of the system and is used for fixing a DC bias level of the system; and
a filter capacitor (CHPF) connected between an input and the switching capacitor circuit network, wherein the filter capacitor and the switching capacitor circuit network together function as a fully integrated on-chip filter,
thereby resulting in a pole frequency depending on a ratio of capacitance of the switching capacitor circuit network and the filter capacitor (CHPF), wherein a capacitance of the filter capacitor is substantially larger than a capacitance of the switching capacitor,
wherein the system is fully integrated on chip using an advanced process node of ≤20 nm.

### Claim 2 (depends on 1)

The system of claim 1, wherein the capacitance of the filter capacitor is 100 times or more larger than the capacitance of the switching capacitor.

### Claim 3 (depends on 1)

The system of claim 1, wherein a resulting pole frequency variation, which varies with process, bias voltage, and temperature, is 10 Hz or lower.

### Claim 4 (depends on 1)

The system of claim 1, wherein a resulting pole frequency variation with input signal swing is removed, thereby providing a linear filtering.

### Claim 5

A method for implementing ultra large resistance on-chip without physical use of a resistor component that is sensitive to pA levels of leakage and that is either not available in advanced process nodes ≤20 nm or prohibitive in die area cost due to lack of high sheet resistance components, to allow integration of a large external de-coupling capacitor for realizing a fully integrated on-chip filter pole that is low in frequency, comprising;
a. using a switching capacitor circuit network to implement the ultra large resistor, wherein the switching capacitor circuit network comprises two switches connected to an input and an output of a switching capacitor (Cs), respectively, in an alternating manner at a selected frequency (fSW), wherein the switching capacitor circuit network is connected to a common mode reference of a system and is used for fixing a DC bias level of the system, and wherein a filter capacitor (CHPF) is connected between an input and the switching capacitor circuit network; and
b. setting a pole frequency to be a function of a ratio of capacitance of the filter capacitor (CHPF) and the switching capacitor (Cs), instead of a RC product, wherein a capacitance of the filter capacitor is substantially larger than a capacitance of the switching capacitor,
thereby attenuating an impact of switching noise by the ratio of capacitance of the capacitors.

### Claim 6 (depends on 5)

The method of claim 5, wherein the capacitance of the filter capacitor is 100 times or more larger than the capacitance of the switching capacitor.

### Claim 7 (depends on 5)

The method of claim 5, wherein a resulting pole frequency variation, which varies with process, bias voltage, and temperature, is 10 Hz or lower.

### Claim 8 (depends on 5)

The method of claim 5, wherein a resulting pole frequency variation with input signal swing is removed, thereby providing a linear filtering.