# US 10,771,043 B2 · Transmit-receive delay element apparatus, method, and applications > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,771,043 B2 - Document ID: US10771043B2 - Status: Granted - Kind: B2 - Application number: 16/085,699 - Filed: 2017-03-17 - Published: 2019-03-07 - Granted: 2020-09-08 - Earliest claimed: 2016-03-17 - Assignees: Cornell University - Applicants: Cornell University - Inventors: Amit Lal; Mamdouh Abdelmejeed; Justin Kuo - Web page: https://patentgrep.com/patent/US10771043B2 ## CPC - H03H 9/30: Time-delay networks - H03H 9/02102: {of temperature influence (cutting angles H03H9/02015)} - H03H 9/131: {consisting of a multilayered structure} - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) ## Abstract A CMOS compatible GHz ultrasonic pulse/echo transmit-receive ultrasonic delay element demonstrating less than <6 ppm stability over time and having a zero-temperature coefficient of delay at two temperatures. The delay element includes one or more CMOS compatible piezoelectric transducers requiring no release step, which transmit and/or receive a GHz-ultrasonic wave packet. The bulk substrate exhibits low loss for the GHz-ultrasonic wave packet transmitted through the substrate and uses the phenomenon of diffraction to retrieve multiple reflections. ## Claims ### Claim 1 An integrated delay apparatus, comprising: a substrate; a piezoelectric transducer integrally disposed on or in the substrate, wherein the piezoelectric transducer is adapted to generate an ultrasonic wave packet having a temporal width from 0.5 to 100 nanoseconds, further wherein the substrate has a thickness, h, that is greater than a spatial width of the ultrasonic wave packet corresponding to the temporal width, further wherein an interface between a bottom surface of the substrate and a medium immediately adjacent the bottom surface of the substrate exhibits an impedance mismatch whereby the bottom surface of the substrate is a reflective surface for the ultrasonic wave packet; and further wherein the integrated delay apparatus is characterized by a delay time, τ, where τ≥2h/vs, where vs is a speed of sound in the substrate. ### Claim 2 (depends on 1) The integrated delay apparatus of claim 1, wherein the interface between the bottom surface of the substrate and the medium immediately adjacent the bottom surface of the substrate is a channel or a cavity in a portion of the bottom surface of the substrate. ### Claim 3 (depends on 1) The integrated delay apparatus of claim 1, wherein the substrate is a material characterized as having a low GHz-ultrasonic wave packet transmission loss. ### Claim 4 (depends on 3) The integrated delay apparatus of claim 3, wherein the substrate is one of Si, SOI, Sapphire, SiC, GaN, a semiconductor, a piezo-material, or a metal. ### Claim 5 (depends on 1) The integrated delay apparatus of claim 1, wherein the piezoelectric transducer is aluminum nitride (AlN). ### Claim 6 (depends on 1) The integrated delay apparatus of claim 1, further comprising a plurality of the substrates including the piezoelectric transducer, wherein the plurality of the substrates are vertically stacked. ### Claim 7 (depends on 1) The integrated delay apparatus of claim 1, wherein the piezoelectric transducer is a transmitting and a receiving transducer. ### Claim 8 (depends on 1) The integrated delay apparatus of claim 1, wherein the piezoelectric transducer is a transmitting transducer, and further comprising at least one receiving piezoelectric transducer integrally disposed on or in the substrate. ### Claim 9 (depends on 8) The integrated delay apparatus of claim 8, wherein the transmitting piezoelectric transducer has a largest transverse surface dimension between 0.5 to 20λ, where λ is a longitudinal wavelength of the ultrasonic wave packet with a carrier frequency, f , where f is between 0.5 to 10 GHz. ### Claim 10 (depends on 8) The integrated delay apparatus of claim 8, wherein the at least one receiving piezoelectric transducer is a lateral distance from the transmitting transducer so as to receive a reflected ultrasonic wave packet. ### Claim 11 (depends on 8) The integrated delay apparatus of claim 8, wherein the at least one receiving piezoelectric transducer comprises an integrally disposed periodic array of receiving piezoelectric transducers. ### Claim 12 (depends on 8) The integrated delay apparatus of claim 8, wherein the at least one receiving piezoelectric transducer is integrally disposed on one of a top surface of the substrate, a bottom surface of the substrate, or in the substrate. ### Claim 13 (depends on 1) The integrated delay apparatus of claim 1, characterized by an Allan deviation of 0.87 ps (<6 ppm). ### Claim 14 (depends on 1) The integrated delay apparatus of claim 1, wherein τ>100 ns. ### Claim 15 (depends on 1) The integrated delay apparatus of claim 1, characterized by a zero-temperature coefficient of delay at two or more temperatures. ### Claim 16 (depends on 1) The integrated delay apparatus of claim 1, characterized in that the integrated delay apparatus is a CMOS integrated delay line. ### Claim 17 An integrated delay apparatus, comprising a substrate; a transmitting piezoelectric transducer integrally disposed on or in the substrate; a receiving piezoelectric transducer integrally disposed on or in the substrate; wherein the transmitting piezoelectric transducer is adapted to generate an ultrasonic was pocket having a temporal width form 0.5 to 100 nanoseconds; further wherein the substrate has a thickness, h, that is greater than a spatial width of the ultrasonic wave packet corresponding to the temporal width; further wherein an interface between a bottom surface of the substrate and a medium immediately adjacent the bottom surface of the substrate exhibits an impedance mismatch whereby the bottom surface of the substrate is a reflective surface for the ultrasonic wave packet; and further wherein the transmitting piezoelectric transducer has a largest transverse surface dimension between 0.5 to 20λ, where λ is a longitudinal wavelength of the ultrasonic wave packet with a carrier frequency, f, where f is between 0.5 to 10 GHz. ### Claim 18 A method for generating a stable delay time, comprising: generating an ultrasonic wave packet having a temporal width from 0.5 to 100 ns with a carrier frequency, f, where f is between 0.5 to 10 GHz; transmitting, using a CMOS-integrated piezoelectric transmit transducer, the ultrasonic wave packet through a bulk substrate; reflecting the transmitted ultrasonic wave packet from a top and/or a bottom surface of the bulk substrate; and detecting, using a CMOS-integrated piezoelectric transmit transducer, the reflected ultrasonic wave packet; wherein the CMOS-integrated piezoelectric receive transducer is laterally located at a distance from the CMOS-integrated piezoelectric transmit transducer such that the delay is temperature stabilized at adjustable temperatures. ### Claim 19 An integrated delay apparatus, comprising: a substrate; a piezoelectric transducer integrally disposed on or in the substrate; wherein the piezoelectric transducer is adapted to generate an ultrasonic wave packet having a temporal width from 0.5 to 100 nanoseconds; further wherein the substrate has a thickness, h, that is greater than a spatial width of the ultrasonic wave packet corresponding to the temporal width; further wherein an interface between a bottom surface of the substrate and a medium immediately adjacent the bottom surface of the substrate exhibits an impedance mismatch whereby the bottom surface of the substrate is a reflective surface for the ultrasonic wave packet; and further wherein the integrated delay apparatus is characterized by an Allan deviation of 0.87 ps (<6 ppm).