# US 10,771,024 B2 · Power amplifier modules including transistor with grading and semiconductor resistor

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- Number: US 10,771,024 B2
- Document ID: US10771024B2
- Status: Granted
- Kind: B2
- Application number: 16/104,114
- Filed: 2018-08-16
- Published: 2019-05-23
- Granted: 2020-09-08
- Earliest claimed: 2012-06-14
- Assignees: Skyworks Solutions, Inc.
- Applicants: Skyworks Solutions, Inc.
- Inventors: Peter J. Zampardi, Jr.; Hongxiao Shao; Tin Myint Ko; Matthew Thomas Ozalas; David Steven Ripley; Philip John Lehtola
- Web page: https://patentgrep.com/patent/US10771024B2

## CPC

- H03F 3/213: in integrated circuits
- H03F 1/0205: {in transistor amplifiers}
- H03F 3/19: with semiconductor devices only
- H03F 3/195: in integrated circuits
- H03F 3/21: with semiconductor devices only {(H03F3/245 takes precedence)}
- H03F 3/245: {with semiconductor devices only}
- H03F 3/60: Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators (H03F3/54 takes precedence)
- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 30/87: FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] {(FETs having Schottky contact on top of heterojunction gate H10D30/801)}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/138: {Pedestal collectors}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 84/01: Manufacture or treatment
- H10D 84/0107: {Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs}
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/05: using Group III-V technology
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 88/01: {Manufacture or treatment}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/092: {Adapting interconnections, e.g. making engineering changes, repairing}
- H10W 70/097: {Cleaning}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- H10W 70/66: Conductive materials thereof
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/0198: {batch processes}
- H10W 74/016: {using moulds}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H03F 1/565: {using inductive elements}
- H03F 3/187: in integrated circuits
- H03F 3/347: in integrated circuits
- H03F 3/45: Differential amplifiers (differential sense amplifiers G11C7/062)
- H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H03F 2200/48: the output of the amplifier being coupled out by a capacitor
- H03F 2200/555: A voltage generating circuit being realised for biasing different circuit elements
- H10D 1/43: Resistors having PN junctions
- H10D 10/80: Heterojunction BJTs
- H10D 30/0612: {of lateral single-gate Schottky FETs}
- H10D 62/124: {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions}
- H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 44/206: {Wires}
- H10W 44/209: {Vertical interconnections, e.g. vias}
- H10W 44/226: {for HF amplifiers}
- H10W 44/231: {Arrangements for applying bias}
- H10W 44/234: {Arrangements for impedance matching}
- H10W 70/69: Insulating materials thereof
- H10W 72/075: {of bond wires}
- H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding}
- H10W 72/07552: {changes in structures or sizes}
- H10W 72/527: {Multiple bond wires having different sizes}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL}
- H03F: AMPLIFIERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

One aspect of this disclosure is a power amplifier module that includes a power amplifier on a substrate and a semiconductor resistor on the substrate. The power amplifier includes a bipolar transistor having a collector, a base, and an emitter. The collector has a doping concentration of at least 3×1016 cm−3 at an interface with the base. The collector also has at least a first grading in which doping concentration increases away from the base. The semiconductor resistor includes a resistive layer that that includes the same material as a layer of the bipolar transistor. Other embodiments of the module are provided along with related methods and components thereof.

## Claims

### Claim 1

A power amplifier module comprising:
a power amplifier on a substrate, the power amplifier including a bipolar transistor having a collector, a base, and an emitter, the collector having a doping concentration of at least 3×1016 cm−3 at an interface with the base, the collector also having a grading in which doping concentration increases away from the base; and
a semiconductor resistor on the substrate, the semiconductor resistor including a resistive layer that includes the same material as a layer of the bipolar transistor.

### Claim 2 (depends on 1)

The power amplifier module of claim 1 wherein the substrate is a gallium arsenide substrate.

### Claim 3 (depends on 1)

The power amplifier module of claim 1 wherein the emitter includes the layer of the bipolar transistor.

### Claim 4 (depends on 1)

The power amplifier module of claim 1 wherein the base includes the layer of the bipolar transistor.

### Claim 5 (depends on 1)

The power amplifier module of claim 1 wherein the bipolar transistor is electrically connected to the semiconductor resistor.

### Claim 6 (depends on 5)

The power amplifier module of claim 5 wherein the semiconductor resistor is configured to provide ballast resistance for the bipolar transistor.

### Claim 7 (depends on 1)

The power amplifier module of claim 1 wherein a semiconductor die includes the bipolar transistor and the semiconductor transistor, and the semiconductor resistor is configured to electrically connect to a circuit that is external to the semiconductor die.

### Claim 8 (depends on 1)

The power amplifier module of claim 1 comprising a first die and a second die, the first die including the bipolar transistor and the semiconductor resistor, and the second die including a bias circuit configured to generate a bias signal based at least partly on an indication of a resistance of the semiconductor resistor and to provide the bias signal to the power amplifier.

### Claim 9 (depends on 1)

The power amplifier module of claim 1 wherein the collector further includes a second grading in which doping concentration increases away from the base at a different rate than in the grading.

### Claim 10 (depends on 1)

The power amplifier module of claim 1 wherein the doping concentration of the collector at the interface with the base is in a range from 3×1016 cm−3 to 9×1016 cm−3.

### Claim 11 (depends on 1)

The power amplifier module of claim 1 wherein the doping concentration of the collector at the interface with the base is in a range from 5×1016 cm−3 to 9×1016 cm−3.

### Claim 12

A power amplifier module comprising:
a power amplifier on a gallium arsenide substrate, the power amplifier including a heterojunction bipolar transistor having a collector, a base, and an emitter, the collector having a doping concentration of at least 3×1016 cm−3 at an interface with the base, the collector also having a grading in which doping concentration increases away from the base; and
a semiconductor resistor on the gallium arsenide substrate, the semiconductor resistor including a resistive layer that includes the same material as a layer of the heterojunction bipolar transistor, and the resistive layer being disposed laterally from and being electrically isolated from the layer of the heterojunction bipolar transistor.

### Claim 13 (depends on 12)

The power amplifier module of claim 12 wherein the base includes the layer of the heterojunction bipolar transistor.

### Claim 14 (depends on 12)

The power amplifier module of claim 12 wherein the emitter includes the layer of the heterojunction bipolar transistor.

### Claim 15 (depends on 12)

The power amplifier module of claim 12 wherein the semiconductor resistor includes a plurality of differently doped gallium arsenide layers.

### Claim 16 (depends on 12)

The power amplifier module of claim 12 wherein the doping concentration of the collector at the interface with the base is at least 5×1016 cm−3.

### Claim 17 (depends on 12)

The power amplifier module of claim 12 wherein the doping concentration of the collector at the interface with the base is in a range from 5×1016 cm−3 to 9×1016 cm−3.

### Claim 18 (depends on 12)

The power amplifier module of claim 12 wherein the collector further includes a second grading in which doping concentration increases away from the base at a different rate than in the grading.

### Claim 19

A power amplifier module comprising:
a power amplifier on a gallium arsenide substrate, the power amplifier including a heterojunction bipolar transistor having a collector, a base, and an emitter, the collector having a doping concentration in a range from 5×1016 cm−3 to 9×1016 cm−3 at an interface with the base, the collector also having a grading in which doping concentration increases away from the base; and
a semiconductor resistor on the gallium arsenide substrate, the semiconductor resistor including a plurality of differently doped gallium arsenide layers, the plurality of differently doped gallium arsenide layers include a resistive layer that includes the same material as a layer of the heterojunction bipolar transistor, and the resistive layer is disposed laterally from and is electrically isolated from the layer of the heterojunction bipolar transistor.

### Claim 20 (depends on 19)

The power amplifier module of claim 19 wherein the semiconductor resistor includes a doped layer of indium gallium phosphate.

### Claim 21 (depends on 19)

The power amplifier module of claim 19 further comprising a bias circuit configured to generate a bias signal based at least partly on an indication of a resistance of the semiconductor resistor and to provide the bias signal to the power amplifier.

### Claim 22 (depends on 19)

The power amplifier module of claim 19 wherein the collector further includes second grading in which doping concentration increases away from the base at a different rate than in the grading.