# US 10,771,017 B2 · Amplifier circuit with low malfunction rate

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- Number: US 10,771,017 B2
- Document ID: US10771017B2
- Status: Granted
- Kind: B2
- Application number: 16/242,011
- Filed: 2019-01-08
- Published: 2020-07-09
- Granted: 2020-09-08
- Earliest claimed: 2019-01-08
- Assignees: Elite Semiconductor Memory Technology Inc.
- Applicants: Elite Semiconductor Memory Technology Inc.
- Inventors: Shao-Ming Sun
- Web page: https://patentgrep.com/patent/US10771017B2

## CPC

- H03F 1/26: Modifications of amplifiers to reduce influence of noise generated by amplifying elements
- H03F 3/217: Class D power amplifiers; Switching amplifiers
- H03F 3/2173: {of the bridge type}
- H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)}
- H03F 3/45475: {using IC blocks as the active amplifying circuit}
- H03F 3/45479: {characterised by the way of common mode signal rejection}
- H03F 3/45636: {by using feedback means (H03F3/45744 takes precedence)}
- H03F 3/45775: {by using cross switches}
- H03F 2203/45512: the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC
- H03F 2203/45614: the IC comprising two cross coupled switches
- H03F: AMPLIFIERS

## Abstract

An amplifier circuit with novel design is provided. The amplifier circuit includes an input stage, a resistor, an output stage, an intermediate stage and a gm circuit. The input stage is coupled to a first supply voltage, and is arranged to receive an input voltage and a feedback current. The resistor is coupled between the input voltage and the input stage. The output stage is coupled to a second supply voltage, and is arranged to provide an output voltage for driving a load. The intermediate stage is coupled between the input stage and the output stage, and includes a level shifter. The gm circuit is coupled to the input stage, and is arranged to compare the input voltage with a common mode voltage, and thereby generates a compensate current for the input stage.

## Claims

### Claim 1

An amplifier circuit, comprising:
an input stage, coupled to a first supply voltage, the input stage arranged to receive a first voltage at a first node;
a first resistor, coupled between an input voltage and the input stage;
an output stage, coupled to a second supply voltage which is different from the first supply voltage, the output stage arranged to provide an output voltage for driving a load;
a second resistor, coupled between the input stage and the output stage;
an intermediate stage, coupled between the input stage and the output stage, the intermediate stage comprising a level shifter; and
a transconductance (gm) circuit, coupled to the input stage rather than the intermediate stage, the gm circuit arranged to compare the first voltage with a common mode voltage, and thereby generates a compensate current to the first node.

### Claim 2 (depends on 1)

The amplifier circuit of claim 1, wherein when the second supply voltage is higher than the first supply voltage, the gm circuit is functioned as a bias current source for sinking the compensate current at the first node.

### Claim 3 (depends on 2)

The amplifier circuit of claim 2, wherein the current flowing through the bias current source is larger than a predetermined current level, and the predetermined current level is determined by the equation:
“
I
P
⁢
R
⁢
E
=
P
⁢
V
⁢
D
⁢
D
-
V
⁢
D
⁢
D
R
⁢
F
”
,
wherein IPRE represents the predetermined current level, PVDD represents the second supply voltage, VDD represents the first supply voltage, and RF represents the resistance of the second resistor.

### Claim 4 (depends on 1)

The amplifier circuit of claim 1, wherein when the second supply voltage is lower than the first supply voltage, the gm circuit is functioned as a bias current source for sourcing the compensate current at the first node.

### Claim 5 (depends on 4)

The amplifier circuit of claim 4, wherein the current flowing through the bias current source is larger than a predetermined current level, and the predetermined current level is determined by the equation:
I
P
⁢
R
⁢
E
=
P
⁢
V
⁢
D
⁢
D
-
V
⁢
D
⁢
D
R
⁢
F
,
wherein IPRE represents the predetermined current level, PVDD represents the second supply voltage, VDD represents the first supply voltage, and RF represents the resistance of the second resistor.

### Claim 6 (depends on 1)

The amplifier circuit of claim 1, wherein the input stage further comprises an amplifier having a positive input end, a negative input end and an output end; the negative input end of the amplifier is coupled to the first node; the positive input end of the amplifier is coupled to the common mode voltage; and the output end of the amplifier is coupled to the negative input end of the amplifier.

### Claim 7 (depends on 6)

The amplifier circuit of claim 6, wherein the input stage further comprises a capacitor coupled between the negative input end and the output end.

### Claim 8 (depends on 1)

The amplifier circuit of claim 1, wherein the common mode voltage (VCM) is equal to VDD/2.

### Claim 9 (depends on 1)

The amplifier circuit of claim 1, wherein the input stage further comprises an amplifier having two input ends, and the gm circuit has a differential input stage and a differential output stage; and the differential input stage and the differential output stage of the gm circuit are coupled to the two input ends of the amplifier.