# US 10,770,971 B2 · Single-input multiple-output (SIMO) converter having a controller with switchable rest states > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,971 B2 - Document ID: US10770971B2 - Status: Granted - Kind: B2 - Application number: 16/428,525 - Filed: 2019-05-31 - Published: 2020-03-26 - Granted: 2020-09-08 - Earliest claimed: 2018-09-26 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Gary Franklin Chard; Ariel Dario Moctezuma; Hasibur Rahman; Alex Kwasi Nyavor Titriku; Srinath Hosur - Web page: https://patentgrep.com/patent/US10770971B2 ## CPC - H02M 3/158: including plural semiconductor devices as final control devices for a single load - H02M 3/157: with digital control - H02M 1/0003: {Details of control, feedback or regulation circuits} - H02M 1/009: {having two or more independently controlled outputs (for DC-DC converter with intermediate AC H02M3/33561)} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract A system includes an inductor and a first switch coupled between a first end of the inductor and a voltage supply node. The system also includes a second switch coupled between the first end of the inductor and a negative output supply node. The system also includes a third switch coupled between a second end of the inductor and a positive output supply node. The system also includes a fourth switch coupled between the second end of the inductor and a ground node. The system also includes a controller coupled to the first, second, third, and fourth switches. The controller is configured to provide an inductor charge mode, a positive boost mode, a negative boost mode, a first rest state involving the first switch, and a second rest state involving the fourth switch. ## Claims ### Claim 1 A system, comprising: an inductor having first and second terminals; a first switch coupled between the first terminal a first end of the inductor and a voltage supply terminal node; a second switch coupled between the first terminal end of the inductor and a negative output supply terminal node; a third switch coupled between the second terminal a second end of the inductor and a positive output supply terminal node; a fourth switch coupled between the second terminal end of the inductor and a ground terminal node; and a controller coupled to the first, second, third, and fourth switches, the controller configured to provide: an inductor charge mode; a positive boost mode; a negative boost mode; a first rest state in which the controller closes the first switch and opens the second, third and fourth switches; and a second rest state in which the controller closes the fourth switch and opens the first, second and third switches. ### Claim 2 (depends on 1) The system of claim 1, wherein: for the inductor charge mode, the controller is configured to close the first and fourth switches and to open the second and third switches; for the positive boost mode, the controller is configured to close the first and third switches and to open the second and fourth switches; and for the negative boost mode, the controller is configured to close the second and fourth switches and to open the first and third switches. ### Claim 3 (depends on 1) The system of claim 1, wherein the controller comprises an asynchronous state machine configured to perform a state machine cycle that includes: starting at one of the first or second rest states; performing at least one boost iteration that includes the inductor charge mode and the positive or negative boost mode; and returning to one of the first or second rest states. ### Claim 4 (depends on 3) The system of claim 3, wherein the controller comprises arbitration logic configured to determine whether the positive boost mode or the negative boost mode is used in a given boost iteration. ### Claim 5 (depends on 4) The system of claim 4, further comprising sense circuitry coupled to the controller, wherein the arbitration logic is configured to determine whether the positive boost mode or the negative boost mode is used in a given boost iteration, responsive to sense signals from the sense circuitry. ### Claim 6 (depends on 5) The system of claim 5, wherein the sense signals include a positive output supply voltage level and a negative output supply voltage level. ### Claim 7 (depends on 3) The system of claim 3, further comprising sense circuitry coupled to the controller, wherein sense signals from the sense circuitry are used to determine when the state machine cycle returns to one of the first or second rest states. ### Claim 8 (depends on 3) The system of claim 3, further comprising enable circuitry coupled to the controller, wherein enable signals from the enable circuitry are used to determine whether the state machine cycle returns to the first rest state or the second rest state. ### Claim 9 (depends on 3) The system of claim 3, wherein the state machine cycle is configured to start in the second rest state by default and to transition to the first rest state after a given boost iteration responsive to a positive output enable signal. ### Claim 10 (depends on 3) The system of claim 3, wherein the asynchronous state machine is configured to switch between single rest state operations and dual rest state operations based on a dual rest state enable signal. ### Claim 11 A single-input multiple-output (SIMO) converter circuit, comprising: a first switch coupled between a first inductor terminal node and a voltage supply terminal; a second switch coupled between the first inductor terminal node and a negative output supply terminal; a third switch coupled between a second inductor terminal node and a positive output supply terminal; a fourth switch coupled between the second inductor terminal node and a ground terminal; and a controller coupled to the first, second, third and fourth switches, the controller configured to switch between: a first rest state in which the controller closes the first switch and opens the second, third and fourth switches; and a second rest state in which the controller closes the fourth switch and opens the first, second and third switches. ### Claim 12 (depends on 11) The SIMO converter circuit of claim 11, wherein: the controller is configured to provide an inductor charge mode by closing the first and fourth switches and opening the second and third switches; the controller is configured to provide a positive boost mode by closing the first and third switches and opening the second and fourth switches; and the controller is configured to provide a negative boost mode by closing the second and fourth switches and opening the first and third switches. ### Claim 13 (depends on 12) The SIMO converter circuit of claim 12, wherein the controller comprises an asynchronous state machine configured to perform a state machine cycle that includes: starting at one of the first or second rest states; performing at least one boost iteration that includes the inductor charge mode and the positive or negative boost mode; and returning to one of the first or second rest states. ### Claim 14 (depends on 13) The SIMO converter circuit of claim 13, further comprising sense circuitry coupled to the controller, wherein the controller comprises arbitration logic configured to determine whether the positive boost mode or the negative boost mode is used in a given boost iteration, responsive to sense signals from the sense circuitry. ### Claim 15 (depends on 13) The SIMO converter circuit of claim 13, further comprising enable circuitry coupled to the controller, wherein enable signals from the enable circuitry are used to determine whether the state machine cycle returns to the first rest state or the second rest state. ### Claim 16 A device, comprising: a first switch coupled between a first inductor terminal and a voltage supply terminal; a second switch coupled between the first inductor terminal and a negative output supply terminal; a third switch coupled between a second inductor terminal and a positive output supply terminal; a fourth switch coupled between the second inductor terminal node and a ground terminal; and an asynchronous state machine coupled to the first, second, third, and fourth switches, the asynchronous state machine configured to switch between: a first rest state in which the controller closes the first switch and opens the second, third and fourth switches; and a second rest state in which the controller closes the fourth switch and opens the first, second and third switches. ### Claim 17 (depends on 16) The device of claim 16, wherein the asynchronous state machine is configured to perform a state machine cycle that includes: starting at one of the first or second rest states; performing at least one boost iteration that includes an inductor charge mode and a positive or negative boost mode; and returning to one of the first or second rest states. ### Claim 18 (depends on 17) The device of claim 17, further comprising sense circuitry coupled to the asynchronous state machine, wherein the asynchronous state machine comprises arbitration logic configured to determine whether the positive boost mode or the negative boost mode is used in a given boost iteration, responsive to sense signals from the sense circuitry. ### Claim 19 (depends on 17) The device of claim 17, further comprising enable circuitry coupled to the controller, wherein at least one enable signal from the enable circuitry is used to determine whether the state machine cycle returns to the first rest state or the second rest state. ### Claim 20 (depends on 19) The device of claim 19, wherein the state machine cycle is configured to start in the second rest state by default and to transition to the first rest state after a given boost iteration responsive to a positive output enable signal. ### Claim 21 (depends on 19) The device of claim 19, wherein the asynchronous state machine is configured to switch between single rest state operations and dual rest state operations based on a dual rest state enable signal.