# US 10,770,892 B2 · Space efficient and power spike resistant ESD power clamp with digitally timed latch

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,770,892 B2
- Document ID: US10770892B2
- Status: Granted
- Kind: B2
- Application number: 15/952,488
- Filed: 2018-04-13
- Published: 2018-08-16
- Granted: 2020-09-08
- Earliest claimed: 2015-11-05
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Alain Loiseau; Andreas D. Stricker
- Web page: https://patentgrep.com/patent/US10770892B2

## CPC

- H02H 9/04: responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T)
- H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits}
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)

## Abstract

Embodiments include a system, apparatus, and method for ESD power clamps. Aspects include protecting a circuit using an ESD power clamp device. The ESD power clamp device includes a trigger circuit having a resistor-capacitor network and an inverter stage circuit, wherein the trigger circuit is configured to detect an ESD event. Aspects of the invention further include a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit controls the timing controlled transistor to prevent the capacitor in the RC network from charging when the timing circuit is initiated. Aspects also include a clamp transistor coupled to the trigger circuit, wherein the clamp transistor is controlled by a signal received from the trigger circuit, and a timing controlled transistor coupled to the trigger circuit and the timing circuit, where the timing controlled transistor switches states based on the output of the timing circuit.

## Claims

### Claim 1

A system for protecting a circuit using a clamping device comprising:
a trigger circuit comprising a resistor-capacitor (RC) network and an inverter stage circuit;
a clamp transistor coupled to the trigger circuit;
a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit comprises an oscillator circuit and a divider circuit; and
the timing controlled transistor coupled to the trigger circuit and the timing circuit.

### Claim 2 (depends on 1)

The system of claim 1, wherein the timing circuit is powered on based on the trigger circuit detecting an electrostatic discharge (ESD) event.

### Claim 3 (depends on 1)

The system of claim 1, wherein the timing circuit is activated based on the trigger circuit detecting an ESD event.

### Claim 4 (depends on 1)

The system of claim 1, further comprising a reset circuit for resetting the divider circuit, wherein the reset circuit is coupled to the divider circuit.

### Claim 5 (depends on 1)

The system of claim 1, further comprising a supplemental transistor serially connected to the timing controlled transistor.

### Claim 6 (depends on 5)

The system of claim 5, wherein the supplemental transistor is coupled to ground.

### Claim 7

A power clamp apparatus for protecting a circuit, comprising:
a trigger circuit comprising an RC network and an inverter stage circuit;
a clamp transistor coupled to the trigger circuit;
a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit comprises an oscillator circuit and a divider circuit, wherein the oscillator circuit provides an input to the divider circuit and the divider circuit being connected to the timing controlled transistor; and
the timing controlled transistor further being coupled to the trigger circuit and the timing circuit.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the timing circuit is powered on based on the trigger circuit detecting an electrostatic discharge (ESD) event.

### Claim 9 (depends on 7)

The apparatus of claim 7, wherein the timing circuit is activated based on the trigger circuit detecting an ESD event.

### Claim 10 (depends on 7)

The apparatus of claim 7, further comprising a reset circuit for resetting the divider circuit, wherein the reset circuit is coupled to the divider circuit.

### Claim 11 (depends on 7)

The apparatus of claim 7, further comprising a supplemental transistor serially connected to the timing controlled transistor.

### Claim 12 (depends on 7)

The system of claim 7, wherein the supplemental transistor is coupled to ground.

### Claim 13

A method for protecting a circuit using a power clamp device, comprising:
detecting an electrostatic discharge (ESD) event by a trigger circuit, wherein the trigger circuit includes an RC network and an inverter stage circuit;
providing, by the trigger circuit, a trigger signal to activate a clamp transistor; and
generating, by a timing circuit, a timing signal to control a timing controlled transistor, wherein the timing circuit comprises an oscillator circuit and a divider circuit.

### Claim 14 (depends on 13)

The method of claim 13, further comprising supplying power to the oscillator circuit and the divider circuit of the timing circuit based on the detection of an ESD event.

### Claim 15 (depends on 13)

The method of claim 13, wherein the timing circuit further comprises a reset circuit coupled to the divider circuit.