# US 10,770,655 B2 · CHIP package

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- Number: US 10,770,655 B2
- Document ID: US10770655B2
- Status: Granted
- Kind: B2
- Application number: 16/542,284
- Filed: 2019-08-15
- Published: 2019-12-05
- Granted: 2020-09-08
- Earliest claimed: 2016-06-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chen-Hua Yu; Kuo-Chung Yee
- Web page: https://patentgrep.com/patent/US10770655B2

## CPC

- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 72/0198: {batch processes}
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 20/0884: {involving forming vias by burying sacrificial pillars in the dielectric parts and removing the pillars}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/01: {Manufacture or treatment}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/072: {of bump connectors}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.

## Claims

### Claim 1

A chip package, comprising:
an integrated circuit chip comprising an active surface;
a plurality of memory chips stacked on the active surface of the integrated circuit chip and electrically connected to the integrated circuit chip;
an insulating encapsulation, laterally encapsulating the plurality of memory chips and partially covering the active surface of the integrated circuit chip; and
a redistribution circuit structure disposed on the plurality of memory chips and the insulating encapsulation, the redistribution circuit structure being electrically connected to the integrated circuit chip and the plurality of memory chips, wherein the active surface of the integrated circuit chip faces the plurality of memory chips.

### Claim 2 (depends on 1)

The chip package as claimed in claim 1 further comprising a controller stacked over the plurality of memory chips, wherein the controller and the plurality of memory chips are laterally encapsulated by the insulating encapsulation.

### Claim 3 (depends on 2)

The chip package as claimed in claim 2, wherein the stacked memory chips and the controller are electrically connected to one another through bumps.

### Claim 4 (depends on 1)

The chip package as claimed in claim 1, wherein the integrated circuit chip further comprises a rear surface opposite to the active surface of the integrated circuit chip, and the integrated circuit chip is electrically connected to the plurality of memory chips through a plurality of bumps.

### Claim 5 (depends on 1)

The chip package as claimed in claim 1, wherein the plurality of memory chips are between the redistribution circuit structure and the integrated circuit chip.

### Claim 6 (depends on 1)

The chip package as claimed in claim 1 further comprising a plurality of conductive pillars penetrating through the insulating encapsulation, wherein the integrated circuit chip is electrically connected to the redistribution circuit structure through the plurality of conductive pillars.

### Claim 7 (depends on 1)

The chip package as claimed in claim 1 further comprising:
a plurality of conductive terminals electrically connected to the redistribution circuit structure, wherein the redistribution circuit structure is between the conductive terminals and the plurality of memory chips.

### Claim 8 (depends on 7)

The chip package as claimed in claim 7 further comprising:
a package circuit substrate, wherein the redistribution circuit structure is electrically connected to the package circuit substrate through the plurality of conductive terminals.

### Claim 9

A chip package, comprising:
an integrated circuit chip comprising an active surface and a rear surface opposite to the active surface, wherein the integrated circuit chip is encapsulated by a first insulating portion;
a plurality of memory chips stacked on the active surface of the integrated circuit chip and the first insulating portion, wherein the plurality of memory chips are electrically connected to the integrated circuit chip, the plurality of memory chips are encapsulated by a second insulating portion; and
a redistribution circuit structure disposed on the rear surface of the integrated circuit chip and the first insulating portion, the redistribution circuit structure being electrically connected to the integrated circuit chip and the plurality of memory chips, wherein the rear surface of the integrated circuit chip faces the redistribution circuit structure.

### Claim 10 (depends on 9)

The chip package as claimed in claim 9, wherein the second insulating portion partially covers the active surface of the integrated circuit chip and the first insulating portion.

### Claim 11 (depends on 9)

The chip package as claimed in claim 9 further comprising:
a plurality of conductive pillars penetrating through the first insulating portion, the plurality of memory chips being electrically connected to the redistribution circuit structure through the conductive pillars; and
a redistribution layer on surfaces of the plurality of memory chips, wherein the integrated circuit chip is electrically connected to the plurality of memory chips through the redistribution circuit structure, the plurality of conductive pillars and the redistribution layer.

### Claim 12 (depends on 9)

The chip package as claimed in claim 9, wherein the integrated circuit chip is between the redistribution circuit structure and the plurality of memory chips.

### Claim 13 (depends on 9)

The chip package as claimed in claim 9 further comprising:
a plurality of conductive terminals electrically connected to the redistribution circuit structure, wherein the redistribution circuit structure is between the conductive terminals and the integrated circuit chip.

### Claim 14 (depends on 13)

The chip package as claimed in claim 13 further comprising:
a package circuit substrate, wherein the redistribution circuit structure is electrically connected to the package circuit substrate through the conductive terminals.

### Claim 15

A chip package, comprising:
an integrated circuit chip comprising an active surface and a rear surface opposite to the active surface, wherein the integrated circuit chip is encapsulated by a first insulating portion;
a plurality of memory chips stacked on the rear surface of the integrated circuit chip and the first insulating portion, wherein the plurality of memory chips are electrically connected to the integrated circuit chip, the plurality of memory chips are encapsulated by a second insulating portion; and
a redistribution circuit structure disposed on the active surface of the integrated circuit chip and the first insulating portion, the redistribution circuit structure being electrically connected to the integrated circuit chip and the plurality of memory chips, wherein the active surface of the integrated circuit chip faces the redistribution circuit structure.

### Claim 16 (depends on 15)

The chip package as claimed in claim 15, wherein the second insulating portion partially covers the rear surface of the integrated circuit chip and the first insulating portion.

### Claim 17 (depends on 15)

The chip package as claimed in claim 15 further comprising:
a plurality of conductive pillars penetrating through the first insulating portion, the plurality of memory chips being electrically connected to the redistribution circuit structure through the conductive pillars; and
a redistribution layer on surfaces of the plurality of memory chips, wherein the integrated circuit chip is electrically connected to the plurality of memory chips through the redistribution circuit structure, the plurality of conductive pillars and the redistribution layer.

### Claim 18 (depends on 15)

The chip package as claimed in claim 15, wherein the integrated circuit chip is between the redistribution circuit structure and the plurality of memory chips.

### Claim 19 (depends on 15)

The chip package as claimed in claim 15 further comprising:
a plurality of conductive terminals electrically connected to the redistribution circuit structure, wherein the redistribution circuit structure is between the conductive terminals and the integrated circuit chip.

### Claim 20 (depends on 19)

The chip package as claimed in claim 19 further comprising:
a package circuit substrate, wherein the redistribution circuit structure is electrically connected to the package circuit substrate through the conductive terminals.