# US 10,770,653 B1 · Selective dielectric deposition to prevent gouging in MRAM

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- Number: US 10,770,653 B1
- Document ID: US10770653B1
- Status: Granted
- Kind: B1
- Application number: 16/515,461
- Filed: 2019-07-18
- Granted: 2020-09-08
- Earliest claimed: 2019-07-18
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Christopher J. Penny; Marc A. Bergendahl; Michael Rizzolo; Christopher J. Waskiewicz
- Web page: https://patentgrep.com/patent/US10770653B1

## CPC

- H10N 50/01: Manufacture or treatment
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method is presented for reducing dielectric gouging during etching processes of a magnetoresistive random access memory (MRAM) structure including an MRAM region and a non-MRAM region. The method includes forming protective layers in the MRAM region to preserve integrity of underlying dielectric layers, forming a bottom electrode in direct contact with the protective layers, and constructing an MRAM pillar over the bottom electrode, wherein the MRAM pillar includes a magnetic tunnel junction (MTJ) stack and a top electrode.

## Claims

### Claim 1

A method for reducing dielectric gouging during etching processes of a magnetoresistive random access memory (MRAM) structure including an MRAM region and a non-MRAM region, the method comprising:
forming a plurality of first conductive lines within a first dielectric at a first metal level;
forming a plurality of second conductive lines within a second dielectric at a second metal level, wherein the first and second metal levels are connected by a via;
depositing a first hardmask and a second hardmask;
etching the first and second hardmasks to expose top surfaces of one or more of the plurality of second conductive lines; and
constructing protective layers in the MRAM region to preserve integrity of underlying dielectric layers, wherein the protective layers are misaligned with respect to conductive lines of the plurality of first and second conductive lines in the first and second metal levels, respectively.

### Claim 2 (depends on 1)

The method of claim 1, wherein a bottom electrode is formed in direct contact with the protective layers.

### Claim 3 (depends on 2)

The method of claim 2, wherein an MRAM pillar is constructed over the bottom electrode, and the MRAM pillar includes a magnetic tunnel junction (MTJ) stack and a top electrode.

### Claim 4 (depends on 3)

The method of claim 3, wherein the protective layers include at least one of silicon oxide, aluminum oxide, or hafnium oxide, or a combination thereof.

### Claim 5 (depends on 4)

The method of claim 4, wherein the protective layers reduce a critical dimension of the bottom electrode to reduce metal resputtering during ion beam etching.

### Claim 6 (depends on 5)

The method of claim 5, wherein the protective layers prevent gouging in the MRAM region.

### Claim 7 (depends on 6)

The method of claim 6, wherein the protective layers are vertically misaligned with respect to encapsulation protectors formed over the bottom electrode.