# US 10,770,638 B2 · Fabrication of interlayer dielectrics with high quality interfaces for quantum computing devices

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- Number: US 10,770,638 B2
- Document ID: US10770638B2
- Status: Granted
- Kind: B2
- Application number: 16/557,116
- Filed: 2019-08-30
- Published: 2019-12-26
- Granted: 2020-09-08
- Earliest claimed: 2019-08-30
- Assignees: Google Inc.
- Applicants: Google LLC
- Inventors: Anthony Edward Megrant
- Web page: https://patentgrep.com/patent/US10770638B2

## CPC

- H10N 60/01: Manufacture or treatment
- G06N 10/40: Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
- H10N 60/80: Constructional details
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

A method includes: providing a first wafer including a first substrate, a first insulator layer on the first substrate, and a first dielectric layer on the first insulator layer; providing a second wafer including a second substrate, a second insulator layer on the second substrate, and a second dielectric layer on the second insulator layer; forming a first superconductor layer on the first dielectric layer; forming a second superconductor layer on the second dielectric layer; joining a surface of the first superconductor layer to a surface of the second superconductor layer to form a wafer stack; and forming a third superconductor layer on exposed first surface of the first dielectric layer.

## Claims

### Claim 1

A method of fabricating a device comprising:
providing a first wafer comprising a first substrate, a first insulator layer on the first substrate, and a first dielectric layer on the first insulator layer;
providing a second wafer comprising a second substrate, a second insulator layer on the second substrate, and a second dielectric layer on the second insulator layer;
forming a first superconductor layer on the first dielectric layer;
forming a second superconductor layer on the second dielectric layer;
joining a surface of the first superconductor layer to a surface of the second superconductor layer to form a wafer stack at an ambient temperature below approximately 150° C.;
identifying an exposed first surface of the first dielectric layer; and
forming a third superconductor layer on the exposed first surface of the first dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein joining the surface of the first superconductor layer to the surface of the second superconductor layer is performed at an ambient temperature below approximately 100° C.

### Claim 3 (depends on 1)

The method of claim 1, wherein joining the surface of the first superconductor layer to the surface of the second superconductor layer is performed at an ambient temperature between approximately 18° C. and approximately 30° C.

### Claim 4 (depends on 1)

The method of claim 1, wherein joining the surface of the first superconductor layer to the surface of the second superconductor layer is performed at an ambient temperature between approximately 18° C. and approximately 26° C.

### Claim 5 (depends on 1)

The method of claim 1, wherein the method is performed at an ambient temperature below 150° C.

### Claim 6 (depends on 1)

The method of claim 1, wherein the method is performed at an ambient temperature of a manufacturing facility in which the device is fabricated.

### Claim 7 (depends on 1)

The method of claim 1, comprising preparing, for joining, the surface of the first superconductor layer and the surface of the second superconductor layer prior to joining the surface of the first superconductor layer to the surface of the second superconductor layer to form the wafer stack.

### Claim 8 (depends on 7)

The method of claim 7, wherein preparing the surface of the first superconductor layer and the surface of the second superconductor layer comprises performing ion milling of the surface of the first superconductor layer and the surface of the second superconductor layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein performing ion milling is performed at an ambient temperature below approximately 150° C.

### Claim 10 (depends on 9)

The method of claim 9, wherein performing ion milling is performed at an ambient temperature between approximately 18° C. and approximately 30° C.

### Claim 11 (depends on 9)

The method of claim 9, wherein the method is performed below a temperature at which hillocks and/or voids form sufficient enough to increase a loss tangent at: an interface between the first superconductor layer and the first dielectric layer; an interface between the second superconductor layer and the second dielectric layer; and an interface between the first superconductor layer and the second superconductor layer.

### Claim 12 (depends on 1)

The method of claim 1, wherein joining the surface of the first superconductor layer to the surface of the second superconductor layer comprises bonding the surface of the first superconductor layer to the surface of the second superconductor layer.

### Claim 13 (depends on 1)

The method of claim 1, wherein joining the surface of the first superconductor layer to the surface of the second superconductor layer is performed under a vacuum in a range of between approximately 10−7 Torr to approximately 10−9 Torr.

### Claim 14 (depends on 1)

The method of claim 1, comprising removing a portion of the first substrate from the wafer stack by performing a dry etch of the first substrate.

### Claim 15 (depends on 14)

The method of claim 14, wherein performing the dry etch comprises exposing the first substrate to a SF6 or XeF2 plasma, and wherein the first insulator layer serves as an etch stop for the dry etch.

### Claim 16 (depends on 1)

The method of claim 1, comprising removing a portion of the first substrate from the wafer stack by performing a wet etch of the first substrate.

### Claim 17 (depends on 1)

The method of claim 1, comprising removing a portion of the first insulator layer from the wafer stack by performing a wet etch of the first insulator layer.

### Claim 18 (depends on 1)

The method of claim 1, further comprising:
forming a through-hole that extends from the third superconductor layer to the first superconductor layer; and
forming a superconductor interconnect in the through-hole that is in contact with the first superconductor layer and the third superconductor layer.

### Claim 19 (depends on 1)

The method of claim 1, wherein the third superconductor layer forms at least part of a quantum device.

### Claim 20 (depends on 19)

The method of claim 19, wherein the quantum device comprises a qubit.

### Claim 21 (depends on 1)

The method of claim 1, wherein the third superconductor layer, the first dielectric layer, and the first superconductor layer form a parallel plate capacitor.