# US 10,770,621 B2 · Semiconductor wafer

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- Number: US 10,770,621 B2
- Document ID: US10770621B2
- Status: Granted
- Kind: B2
- Application number: 16/092,007
- Filed: 2017-04-07
- Published: 2019-04-18
- Granted: 2020-09-08
- Earliest claimed: 2016-04-08
- Assignees: Stanley Electric Co., Ltd.
- Applicants: Stanley Electric Co., Ltd.
- Inventors: Toshiyuki Obata
- Web page: https://patentgrep.com/patent/US10770621B2

## CPC

- H10H 20/819: characterised by their shape, e.g. curved or truncated substrates
- H10H 20/01335: {the light-emitting regions comprising nitride materials}
- H10H 20/821: of the light-emitting regions, e.g. non-planar junctions
- H10H 20/825: containing nitrogen, e.g. GaN
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/2921: {being crystalline insulating materials}
- H10P 14/2926: {Crystal orientations}
- H10P 14/3216: {Nitrides}
- H10P 14/3251: {consisting of three or more layers}
- H10P 14/3416: {Nitrides}
- H10P 14/3442: {N-type}
- H10P 14/3444: {P-type}
- H10H 20/01: Manufacture or treatment
- H10H 20/8162: {Current-blocking structures}
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor wafer has, on one surface of a sapphire substrate, an element layer including an n-type layer, an active layer, and a p-type layer, and is characterized in that the surface of the element layer is bent in a convex way, and the curvature thereof is 530-800 km−1.

## Claims

### Claim 1

A semiconductor wafer comprising:
an element layer comprising at least three layers including an n-type layer, an active layer, and a p-type layer on one surface of a sapphire substrate, wherein the element layer is made of a group III nitride single crystal layer,
wherein a surface of the element layer is bent in a convex way, and a curvature thereof is 530 km−1 to 800 km−1, and
wherein the group III nitride single crystal layer is made of an AlGaInN layer satisfying a composition represented by AlxInyGazN, wherein x, v, and z are rational numbers satisfying 0.3≤x≤1.0, 0≤y 0.7, and 0≤z≤0.7, and x+y+z=1.0.

### Claim 2 (depends on 1)

The semiconductor wafer according to claim 1, wherein a plane of the sapphire substrate on which the element layer is formed is a (0001) plane.

### Claim 3

A semiconductor wafer comprising:
an element layer comprising at least three layers including an n-type layer, an active layer, and a p-type layer on one surface of a sapphire substrate,
wherein a surface of the element layer is bent in a convex way, and a curvature thereof is 530 km−1 to 800 km−1 and
wherein a buffer layer made of AlxInyGazN, wherein x, y, and z are rational numbers satisfying 0.8≤x≤1.0, 0≤y≤0.2, and 0≤z≤0.2, and x+y+z=1.0 included between the one surface of the sapphire substrate and the element layer.

### Claim 4 (depends on 3)

The semiconductor wafer according to claim 3, wherein the buffer layer includes at least two layers of a first buffer layer and a second buffer layer.

### Claim 5 (depends on 4)

The semiconductor wafer according to claim 4, wherein a plane of the sapphire substrate on which the element layer is formed is a (0001) plane.

### Claim 6 (depends on 3)

The semiconductor wafer according to claim 3, wherein a plane of the sapphire substrate on which the element layer is formed is a (0001) plane.

### Claim 7

A semiconductor wafer comprising group III nitride single crystal layers on one surface of a sapphire substrate, comprising:
a sapphire substrate having one surface of predetermined plane orientation;
an element layer having a laminated structure including an n-type layer made of group III nitride single crystal layer, an active layer made of group III nitride single crystal layer, and a p-type layer made of group III nitride single crystal layer, is on the one surface of the sapphire substrate;
wherein the active layer is positioned between the n-type layer and the p-type layer,
wherein the group III nitride single crystal layers comprise an AlGaInN layer satisfying a composition represented by AlxInyGazN, wherein x, y, and z are rational numbers satisfying 0.3≤x≤1.0, 0≤y 0.7, and 0≤z≤0.7, and x+y+z=1.0, and
wherein a surface of the element layer is bent in a convex way, and a curvature thereof is 530 km−1 to 800 km−1.

### Claim 8 (depends on 7)

The semiconductor wafer according to claim 7, wherein a buffer layer made of AlxInyGazN, wherein x, y, and z are rational numbers satisfying 0.8≤x≤1.0, 0≤y≤0.2, and 0≤z≤0.2, and x+y+z=1.0, is included between the one surface of the sapphire substrate and the element layer.

### Claim 9 (depends on 8)

The semiconductor wafer according to claim 8, wherein the buffer layer includes at least two layers of a first buffer layer and a second buffer layer.

### Claim 10 (depends on 7)

The semiconductor wafer according to claim 7, wherein a plane of the sapphire substrate on which the element layer is formed is a (0001) plane.

### Claim 11 (depends on 7)

A semiconductor wafer with an element circuit, comprising an n-electrode on the n-type layer and a p-electrode on the p-type layer of the semiconductor wafer according to claim 7.

### Claim 12

A semiconductor light emitting device comprising group III nitride single crystal layers on one surface of a sapphire substrate, comprising:
a sapphire substrate having one surface of predetermined plane orientation;
an element layer having laminated structure including an n-type layer made of group III nitride single crystal layer, an active layer made of group III nitride single crystal layer, and a p-type layer made of group III nitride single crystal layer, is on the one surface of the sapphire substrate,
wherein the active layer is positioned between the n-type layer and the p-type layer,
wherein the group III nitride single crystal layers comprise an AlGaInN layer satisfying a composition represented by AlxInyGazN, wherein x, y, and z are rational numbers satisfying 0.3≤x≤1.0, 0≤y 0.7, and 0≤z≤0.7, and x+y+z=1.0,
wherein an n-electrode is on the n-type layer and a p-electrode is on the p-type layer, and
wherein a surface of the element layer is bent in a convex way, and a curvature thereof is 530 km−1 to 800 km−1.

### Claim 13 (depends on 12)

The semiconductor light emitting device according to claim 12, wherein a buffer layer made of AlxInyGazN, wherein x, y, and z are rational numbers satisfying 0.8≤x≤1.0, 0≤y≤0.2, and 0≤z≤0.2, and x+y+z=1.0, is included between the one surface of the sapphire substrate and the element layer.

### Claim 14 (depends on 13)

The semiconductor wafer according to claim 13, wherein the buffer layer includes at least two layers of a first buffer layer and a second buffer layer.

### Claim 15 (depends on 13)

The semiconductor light emitting device according to claim 13, wherein an emission peak wavelength is in an ultraviolet region.

### Claim 16 (depends on 14)

The semiconductor light emitting device according to claim 14, wherein an emission peak wavelength is in a range of 200 nm to 350 nm.

### Claim 17 (depends on 12)

The semiconductor light emitting device according to claim 12, wherein an emission peak wavelength is in an ultraviolet region.

### Claim 18 (depends on 12)

The semiconductor light emitting device according to claim 12, wherein an emission peak wavelength is in a range of 200 nm to 350 nm.

### Claim 19

A method for producing a semiconductor light emitting device, comprising:
preparing a semiconductor wafer comprising an element layer made of at least three layers including an n-type layer, an active layer, and a p-type layer on one surface of a sapphire substrate, wherein:
the element layer is made of a group III nitride single crystal layer,
the group III nitride single crystal layer is made of an AlGaInN layer satisfying a composition represented by AlxInyGazN, wherein x, y, and z are rational numbers satisfying 0.3≤x≤1.0, 0≤y 0.7, and 0≤z≤0.7, and x+y+z=1.0, and
a surface of the element layer is bent in a convex way, and a curvature thereof is 530 km−1 to 800 km−1;
preparing a semiconductor wafer with an element circuit, by forming an n-electrode on the n-type layer and a p-electrode on the p-type layer of the semiconductor wafer; and
cutting the semiconductor wafer with an element circuit into semiconductor chips.