# US 10,770,606 B2 · Solar array system and method of manufacturing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,606 B2 - Document ID: US10770606B2 - Status: Granted - Kind: B2 - Application number: 15/819,196 - Filed: 2017-11-21 - Published: 2018-04-05 - Granted: 2020-09-08 - Earliest claimed: 2015-07-27 - Assignees: Sierra Nevada Corporation - Applicants: Sierra Nevada Corporation - Inventors: Brian Anthony; Rodney Dobson; Matthew Johnson; Scott Christiansen; L. Eric Ruhl - Web page: https://patentgrep.com/patent/US10770606B2 ## CPC - H10F 77/80: Arrangements for preventing damage to photovoltaic cells caused by corpuscular radiation, e.g. for space applications - B64G 1/443: {Photovoltaic cell arrays} - H10F 19/00: Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules - H10F 19/75: the bypass diodes being integrated or directly associated with the photovoltaic cells, e.g. formed in or on the same substrate - H10F 19/80: Encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells - H10F 19/902: {for series or parallel connection of photovoltaic cells} - H10F 19/908: {for back-contact photovoltaic cells} - H10F 71/00: Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) - H10F 71/136: {Singulating, e.g. dicing} - H10F 77/219: {Arrangements for electrodes of back-contact photovoltaic cells} - H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10P 72/0428: {Apparatus for mechanical treatment or grinding or cutting} - H10P 72/0438: {Apparatus for making assemblies not otherwise provided for, e.g. package constructions} - Y02E 10/50: Photovoltaic [PV] energy - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - B64G: COSMONAUTICS; VEHICLES OR EQUIPMENT THEREFOR - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION ## Abstract A space-grade solar array includes relatively small cells with integrated wiring embedded into or incorporated directly onto a printed circuit board. The integrated wiring provides an interface for solar cells having back side electrical contacts. The single side contacts enable the use of pick and place (PnP) technology in manufacturing the space-grade solar array. The solar cell is easily and efficiently packaged and electrically interconnected with other solar cells on a solar panel such as by using PnP process. The back side contacts are matched from a size and positioning standpoint to corresponding contacts on the printed circuit board. ## Claims ### Claim 1 A method of manufacturing a space-grade solar array, comprising: dicing a multi-junction solar wafer having a plurality of solar cells to form a plurality of diced multi-junction solar cells, wherein each solar cell already has a positive electrical contact and a negative electrical contact both located on a common, back side of the solar cell; using a pick and place robot to position the diced solar cells onto a printed circuit board with the back side of each diced solar cell in contact with a front side of the printed circuit board such that the positive electrical contact and the negative electrical contact of each diced solar cell electrically couples to a corresponding electrical contact of the printed circuit board, and wherein the printed circuit board has electrical traces that include solar cell-to-solar cell interconnect wiring and bypass and blocking diodes, and wherein the positive electrical contact and the negative electrical contact of each diced solar cell has a coefficient of thermal expansion that matches a coefficient of thermal expansion of the electrical contact of the printed circuit board; and after the plurality of diced solar cells are positioned on the printed circuit board, covering the plurality of diced solar cells with a coverglass material while the diced solar cells are positioned on the printed circuit board and bonding the coverglass material to the plurality of diced solar cells. ### Claim 2 (depends on 1) The method of claim 1, wherein the printed circuit board is rigid. ### Claim 3 (depends on 1) The method of claim 1, wherein the printed circuit board is flexible. ### Claim 4 (depends on 1) The method of claim 1, wherein the printed circuit board serves as a solar array panel. ### Claim 5 (depends on 1) The method of claim 1, further comprising positioning the printed circuit board with the solar cells onto a solar array panel. ### Claim 6 (depends on 1) The method of claim 1, wherein the solar cell wafer is cut into solar cells that are no larger than 20 cm2. ### Claim 7 (depends on 1) The method of claim 1, further comprising locating the bypass and blocking diodes onto a back side of the printed circuit board. ### Claim 8 (depends on 1) The method of claim 1, further comprising using a pick and place robot to position the solar cells onto the printed circuit board. ### Claim 9 (depends on 1) The method of claim 1, wherein a pick and place robot is used automatically to position the solar cells onto the printed circuit board without human intervention. ### Claim 10 (depends on 1) The method of claim 1, wherein both the positive electrical contact and the negative electrical contact are exposed contacts. ### Claim 11 (depends on 1) The method of claim 1, wherein the positive electrical contact and the negative electrical contact of each diced solar cell has a size that matches a size of respective electrical contact of the printed circuit board. ### Claim 12 (depends on 1) The method of claim 1, wherein only the diced solar cells are positioned on the printed circuit board. ### Claim 13 (depends on 12) The method of claim 12, further comprising removing and replacing a single solar cell from the printed circuit board. ### Claim 14 (depends on 12) The method of claim 12, further comprising removing and replacing a single solar cell from the printed circuit board without affecting a power capability of the entire solar array. ### Claim 15 (depends on 12) The method of claim 12, further comprising placing only bypass and blocking diodes on a back side of the printed circuit board. ### Claim 16 (depends on 1) The method of claim 1, further comprising removing and replacing a single solar cell from the printed circuit board. ### Claim 17 A method of manufacturing a space-grade solar array, comprising: dicing a multi junction solar wafer having a plurality of solar cells to form a diced multi-junction solar cell, wherein the diced solar cell already has a positive electrical contact and a negative electrical contact both located on a common, back side of the diced solar cell; covering the diced solar cell with a protective coverglass, wherein the coverglass is a space-grade, radiation protective coverglass; using a pick and place robot to position the diced solar cells onto a printed circuit board with the back side of the diced solar cell in contact with a front side of the printed circuit board such that the positive electrical contact and the negative electrical contact of the diced solar cell electrically couples to a corresponding electrical contact of the printed circuit board, and wherein the printed circuit board has electrical traces that include solar cell-to-solar cell interconnect wiring and bypass and blocking diodes, and wherein the positive electrical contact and the negative electrical contact of the diced solar cell has a coefficient of thermal expansion that matches a coefficient of thermal expansion of the electrical contact of the printed circuit board, wherein only the diced solar cells are positioned on the printed circuit board. ### Claim 18 (depends on 17) The method of claim 17, wherein the printed circuit board is rigid. ### Claim 19 (depends on 17) The method of claim 17, wherein the printed circuit board is flexible. ### Claim 20 (depends on 17) The method of claim 17, wherein the printed circuit board serves as a solar array panel. ### Claim 21 (depends on 17) The method of claim 17, further comprising positioning the printed circuit board with the solar cells onto a solar array panel. ### Claim 22 (depends on 17) The method of claim 17, wherein the solar cell wafer is cut into solar cells that are no larger than 20 cm2. ### Claim 23 (depends on 17) The method of claim 17, further comprising locating the bypass and blocking diodes onto a back side of the printed circuit board. ### Claim 24 (depends on 17) The method of claim 17, further comprising using a pick and place robot to position the solar cells onto the printed circuit board. ### Claim 25 (depends on 17) The method of claim 17, wherein a pick and place robot is used automatically to position the solar cells onto the printed circuit board without human intervention. ### Claim 26 (depends on 17) The method of claim 17, wherein both the positive electrical contact and the negative electrical contact are exposed contacts.