# US 10,770,598 B2 · Memory devices and methods of manufacture thereof

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- Number: US 10,770,598 B2
- Document ID: US10770598B2
- Status: Granted
- Kind: B2
- Application number: 16/684,721
- Filed: 2019-11-15
- Published: 2020-03-12
- Granted: 2020-09-08
- Earliest claimed: 2012-12-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Alexander Kalnitsky; Hsiao-Chin Tuan; Felix Ying-Kit Tsui; Hau-Yan Lu
- Web page: https://patentgrep.com/patent/US10770598B2

## CPC

- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- G11C 16/0441: {comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates}
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10B 41/60: the control gate being a doped region, e.g. single-poly memory cell
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.

## Claims

### Claim 1

A method of manufacturing a memory device, the method comprising:
forming a first patterned mask over a substrate;
patterning the substrate to form a first recess and a second recess using the first patterned mask as a mask;
filling the first recess and the second recess with a dielectric material to form a first isolation region and a second isolation region, the first isolation region being interposed between a first region of the substrate and a second region of the substrate, the second isolation region interposed between the second region and a third region of the substrate;
forming a second patterned mask over the substrate;
patterning the substrate to form a third recess using the second patterned mask as a mask, wherein the third recess is in the first region;
forming a dielectric layer over the first region, the second region, and the third region of the substrate, the dielectric layer extending into the third recess; and
forming a conductive electrode over the dielectric layer in the first region, the second region, and the third region of the substrate, wherein the conductive electrode comprises a plate of a first capacitor in the first region, a gate of a transistor in the second region, and a plate of a second capacitor in the third region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first recess and the second recess are formed prior to forming the third recess.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first recess and the second recess are formed after to forming the third recess.

### Claim 4 (depends on 1)

The method of claim 1, further comprising forming a doped region in the substrate, the doped region extending along sidewalls of the third recess.

### Claim 5 (depends on 4)

The method of claim 4, wherein the doped region surrounds the third recess in a plan view.

### Claim 6 (depends on 1)

The method of claim 1, wherein the dielectric layer and the conductive electrode extend continuously from the first isolation region to the second isolation region.

### Claim 7 (depends on 1)

The method of claim 1, wherein the dielectric layer and the conductive electrode extend from the first region to the second region, and from the second region to the third region.

### Claim 8

A method of manufacturing a memory device, the method comprising:
patterning a substrate to form a first recess, a second recess, and third recess using one or more patterned masks;
filling the first recess, the second recess, and the third recess with a first dielectric material, the first dielectric material in the first recess forming a first isolation region, the first dielectric material in the second recess forming a second isolation region, the first isolation region being interposed between a first region of the substrate and a second region of the substrate, the second isolation region interposed between the second region and a third region of the substrate, wherein the third recess is in the first region;
removing the first dielectric material in the third recess;
doping the substrate along sidewalls of the third recess;
forming source/drain regions in the second region;
forming a dielectric layer over the first region, the second region, and the third region; and
forming a conductive layer over the dielectric layer in the first region, the second region, and the third region of the substrate, wherein the conductive layer comprises a plate of a first capacitor in the first region, a gate of a transistor in the second region, and a plate of a second capacitor in the third region.

### Claim 9 (depends on 8)

The method of claim 8, wherein the third recess is V-shape.

### Claim 10 (depends on 9)

The method of claim 9, wherein an upper periphery of the V-shape has a length and width is less than or equal to 0.5 μm.

### Claim 11 (depends on 8)

The method of claim 8, wherein forming the conductive layer in the first region, the second region, and the third region comprises forming the conductive layer to have a first length in the first region different than a second length in the third region.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming the conductive layer in the first region, the second region, and the third region comprises forming the conductive layer to have a third length in the second region different than the second length in the third region.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first length and the third length is less than the second length.

### Claim 14

A method of manufacturing a memory device, the method comprising:
forming a first isolation region and a second isolation region in a substrate, the first isolation region being interposed between a first region of the substrate and a second region of the substrate, the second isolation region interposed between the second region and a third region of the substrate;
forming a patterned mask over the substrate;
patterning the substrate to form a recess using the patterned mask as a mask, wherein the recess is in the first region;
forming a dielectric layer over the first region, the second region, and the third region of the substrate, the dielectric layer extending into the recess; and
forming a conductive electrode over the dielectric layer in the first region, the second region, and the third region of the substrate, wherein the conductive electrode comprises a plate of a first capacitor in the first region, a gate of a transistor in the second region, and a plate of a second capacitor in the third region.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first isolation region and the second isolation region are formed prior to forming the recess.

### Claim 16 (depends on 14)

The method of claim 14, wherein the first isolation region and the second isolation region are formed after to forming the recess.

### Claim 17 (depends on 14)

The method of claim 14, further comprising forming a doped region in the substrate, the doped region extending along sidewalls of the recess.

### Claim 18 (depends on 17)

The method of claim 17, wherein the doped region surrounds the recess in a plan view.

### Claim 19 (depends on 14)

The method of claim 14, wherein the dielectric layer and the conductive electrode extend continuously from the first isolation region to the second isolation region.

### Claim 20 (depends on 14)

The method of claim 14, wherein the dielectric layer and the conductive electrode extend from the first region to the second region, and from the second region to the third region.