# US 10,770,594 B2 · Gate-all-around fin device

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- Number: US 10,770,594 B2
- Document ID: US10770594B2
- Status: Granted
- Kind: B2
- Application number: 16/034,576
- Filed: 2018-07-13
- Published: 2018-11-22
- Granted: 2020-09-08
- Earliest claimed: 2014-11-19
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: John B. Campi, Jr.; Robert J. Gauthier, Jr.; Rahul Mishra; Souvick Mitra; Mujahid Muhammad
- Web page: https://patentgrep.com/patent/US10770594B2

## CPC

- B29C 48/49: using two or more extruders to feed one die or nozzle
- B29C 37/0025: {Applying surface layers, e.g. coatings, decorative layers, printed layers, to articles during shaping, e.g. in-mould printing (moulding on preformed layers as inserts B29C70/68; applying fluent material to surfaces in general B05)}
- B29C 48/21: the layers being joined at their surfaces
- B32B 3/08: characterised by added members at particular parts {(layer formed of separate pieces of material which are juxtaposed side-by-side B32B3/14, B32B3/18)}
- B32B 27/00: Layered products comprising {a layer of} synthetic resin {(fibrous or filamentary layer made of a synthetic resin B32B5/02; particulate layer made of a synthetic resin B32B5/16; foamed layer made of a synthetic resin B32B5/18)}
- B32B 27/08: of synthetic resin
- B32B 27/28: comprising synthetic resins not wholly covered by any one of the sub-groups {B32B27/30 - B32B27/42}
- B32B 27/306: {comprising vinyl acetate or vinyl alcohol (co)polymers}
- B32B 27/308: {comprising acrylic (co)polymers}
- B32B 27/32: comprising polyolefins {(comprising vinyl (co)polymers or acrylic (co)polymers B32B27/30)}
- B32B 27/34: comprising polyamides
- B32B 27/36: comprising polyesters
- H01G 4/005: Electrodes
- H01G 4/14: Organic dielectrics
- H01G 4/20: using combinations of dielectrics from more than one of groups H01G4/02 - H01G4/06 (H01G4/12 takes precedence)
- H01G 4/206: {inorganic and synthetic material}
- H01G 4/228: Terminals
- H01G 4/30: Stacked capacitors (H01G4/33 takes precedence)
- H01G 4/33: Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/0289: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/658: {having trench gate electrodes}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/663: {having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS}
- H10D 30/665: {having edge termination structures}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/153: {Impurity concentrations or distributions}
- H10D 62/154: {Dispositions}
- H10D 62/155: {Shapes (cell layout of DMOS H10D62/127)}
- H10D 62/158: {Dispositions}
- H10D 62/159: {Shapes}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0156: {Manufacturing their doped wells}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/835: {comprising LDMOS}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- B29K 2023/12: {PP, i.e. polypropylene}
- B29K 2105/16: Fillers
- B29K 2507/04: Carbon
- B29K 2995/0005: Conductive
- B29K 2995/0007: Insulating
- B29L 2009/003: {comprising a metal layer}
- B29L 2009/005: {coated}
- B29L 2031/34: Electrical apparatus, e.g. sparking plugs or parts thereof
- B32B 2262/106: Carbon fibres, e.g. graphite fibres
- B32B 2264/105: Metal
- B32B 2264/12: Mixture of at least two particles made of different materials
- B32B 2270/00: Resin or rubber layer containing a blend of at least two different polymers
- B32B 2274/00: Thermoplastic elastomer material
- B32B 2307/202: Conductive
- B32B 2307/204: Di-electric
- B32B 2307/206: Insulating
- B32B 2307/518: bi-axially
- B32B 2307/732: Dimensional properties
- B32B 2457/16: Capacitors
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- B29C: SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING (making preforms B29B11/00; making laminated products by combining previously unconnected layers which become one product whose layers will remain together B32B37/00 - B32B41/00)
- B32B: LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B29K: INDEXING SCHEME ASSOCIATED WITH SUBCLASSES B29B, B29C OR B29D, RELATING TO MOULDING MATERIALS OR TO MATERIALS FOR {MOULDS, } REINFORCEMENTS, FILLERS OR PREFORMED PARTS, e.g. INSERTS
- B29L: INDEXING SCHEME ASSOCIATED WITH SUBCLASS B29C, RELATING TO PARTICULAR ARTICLES

## Abstract

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

## Claims

### Claim 1

A method comprising:
forming a doped well in a substrate of a first conductivity type;
forming a doped continuous well of a second conductivity type in the substrate of the first conductivity type; and
forming, over the doped continuous well of the second conductivity type, a floating p− fin comprising a p+ body contact formed directly on the floating p− fin,
wherein the doped well is of the first conductivity type.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming a shallow trench isolation (STI) structure in the doped well.

### Claim 3 (depends on 1)

The method of claim 1, wherein the doped continuous well of the second conductivity type is formed as a continuous deep N-well and the doped well of the first conductivity type is formed as a P-well.

### Claim 4 (depends on 1)

The method of claim 1, wherein the doped continuous well of the second conductivity type is formed as a continuous shallow N-well and the doped well of the first conductivity type is formed as a P-well.

### Claim 5

A structure comprising:
a substrate of a first conductivity type;
a doped well in the substrate of the first conductivity type;
a doped continuous well of a second conductivity type in the substrate of the first conductivity type; and
a floating p− fin over the doped continuous well of the second conductivity type comprising a p+ body contact formed directly on the floating p− fin,
wherein the doped well is of the first conductivity type.

### Claim 6 (depends on 5)

The structure of claim 5, further comprising a shallow trench isolation (STI) structure formed in the doped well.

### Claim 7 (depends on 5)

The structure of claim 5, wherein the doped continuous well of the second conductivity type is a continuous deep N-well and the doped well of the first conductivity type is a P-well.

### Claim 8 (depends on 5)

The structure of claim 5, wherein the doped continuous well of the second conductivity type is a continuous shallow N-well and the doped well of the first conductivity type is a P-well.