# US 10,770,590 B2 · Semiconductor structures and fabrication methods thereof

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- Number: US 10,770,590 B2
- Document ID: US10770590B2
- Status: Granted
- Kind: B2
- Application number: 16/114,857
- Filed: 2018-08-28
- Published: 2019-02-28
- Granted: 2020-09-08
- Earliest claimed: 2017-08-31
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; SMIC New Technology Research and Development (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; SMIC New Technology Research and Development (Shanghai) Corporation
- Inventors: Fei Zhou
- Web page: https://patentgrep.com/patent/US10770590B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/517: {characterised by the conducting layers}
- H10D 64/679: {comprising air gaps}
- H10D 64/687: {having cavities, e.g. porous gate dielectrics having gasses therein}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/48: Insulating materials thereof
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating a semiconductor structure includes providing a base substrate, including a substrate, a plurality of gate structures formed on the substrate, and a cap layer formed on the plurality of gate structures; removing the cap layer to form a trench on each gate structure; and forming a substitution layer in the trench. The dielectric constant of the substitution layer is smaller than the dielectric constant of the cap layer.

## Claims

### Claim 1

A method for fabricating a semiconductor structure, comprising:
providing a base substrate, including a substrate, a plurality of gate structures formed on the substrate, and a cap layer formed on the plurality of gate structures, wherein each gate structure includes a gate dielectric layer formed on the substrate, a work function layer formed on the gate dielectric layer, and a gate electrode layer formed on the work function layer;
forming a sidewall spacer is on each sidewall surface of the gate structure;
removing the cap layer, a top portion of the gate dielectric layer, a top portion of the work function layer, a portion of a top portion of the sidewall spacer to form a trench on each gate structure, wherein a top surface of a remaining portion of the gate dielectric layer, a top surface of a remaining portion of the work function layer, and a top surface of a bottom portion of the sidewall spacer are coplanar with each other; and
forming a substitution layer in the trench, wherein:
a dielectric constant of the substitution layer is smaller than a dielectric constant of the cap layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein:
the cap layer is made of silicon nitride; and
the dielectric constant of the substitution layer is smaller than a dielectric constant of SiNx.

### Claim 3 (depends on 1)

The method according to claim 1, wherein:
the dielectric constant of the substitution layer is in a range of approximately 2.5 to 3.9.

### Claim 4 (depends on 1)

The method according to claim 1, wherein:
the substitution layer is made of silicon oxide.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the base substrate further includes:
a source/drain doped region formed in the substrate on each side of the gate structure; and
an interlayer dielectric layer formed on the source/drain doped region, wherein, after providing the base substrate and prior to removing the cap layer, the method further includes:
forming a contact hole in the interlayer dielectric layer using the cap layer as a mask to expose the source/drain doped region at a bottom of the contact hole; and
forming a plug in the contact hole.

### Claim 6 (depends on 5)

The method according to claim 5, wherein forming the substitution layer in the trench includes:
forming a substitution material layer in the trench, wherein the substitution material layer also covers the interlayer dielectric layer; and
forming the substitution layer by removing a portion of the substitution material layer formed above a top surface of the interlayer dielectric layer.

### Claim 7 (depends on 6)

The method according to claim 6, wherein:
the substitution material layer formed in the trench contains a plurality of internal cavities;
the substitution layer formed by removing the portion of the substitution material layer formed above the top surface of the interlayer dielectric layer contains a plurality of internal cavities; and
the substitution material layer is formed by one or both of an atmospheric pressure chemical vapor deposition (APCVD) process and a subatmospheric pressure chemical vapor deposition (SACVD) process.

### Claim 8 (depends on 7)

The method according to claim 7, wherein:
the plurality of internal cavities are formed in the substitution layer on top of the remaining portion of the gate dielectric layer and the remaining portion of the work function layer.

### Claim 9 (depends on 6)

The method according to claim 6, wherein:
the substitution material layer fills up the trench;
the substitution layer, formed by removing the portion of the substitution material layer above the top surface of the interlayer dielectric layer, fills up the trench; and
the substitution material layer is formed by one or both of a plasma enhanced chemical vapor deposition (PECVD) process and a high density plasma chemical vapor deposition (HDPCVD) process.

### Claim 10 (depends on 1)

The method according to claim 1, wherein:
the work function layer and the gate dielectric layer also cover sidewall surfaces of the gate electrode layer; and
the trench exposes a top surface of the gate electrode layer as well as a portion of the sidewall surfaces of the gate electrode layer.

### Claim 11 (depends on 10)

The method according to claim 10, wherein:
a ratio of a height of the portion of the sidewall surfaces of the gate electrode layer exposed at a bottom of the trench to a height of the gate electrode layer is in a range of approximately 1:6 to 1:1.

### Claim 12 (depends on 1)

The method according to claim 1, wherein:
a thickness of the removed portion of the sidewall spacer is in a range of approximately 10 Å to 100 Å.

### Claim 13 (depends on 1)

The method according to claim 1, wherein:
the substitution layer is formed on the remaining portion of the gate dielectric layer, the top surface of the remaining portion of the work function layer, and the top surface of the bottom portion of the sidewall spacer.

### Claim 14 (depends on 1)

The method according to claim 1, wherein:
a remaining portion of the top portion of the sidewall spacer has a uniform first thickness,
the bottom portion of the sidewall spacer has a uniform second thickness, and
the uniform first thickness is smaller than the uniform second thickness.