# US 10,770,585 B2 · Self-aligned buried contact for vertical field-effect transistor and method of production thereof

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- Number: US 10,770,585 B2
- Document ID: US10770585B2
- Status: Granted
- Kind: B2
- Application number: 16/139,917
- Filed: 2018-09-24
- Published: 2020-03-26
- Granted: 2020-09-08
- Earliest claimed: 2018-09-24
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Ruilong Xie; Chanro Park; Andre Labonte; Daniel Chanemougame
- Web page: https://patentgrep.com/patent/US10770585B2

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10W 20/48: Insulating materials thereof
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device including a self-aligned buried contact between spacer liners and isolated from a pull down (PD)/pull-up (PU) shared gate and an n-channel field-effect transistor (NFET) pass gate (PG) gate and method of production thereof. Embodiments include first and second high-k/metal gate (HKMG) structures over a first portion of a substrate, and a third HKMG structure over a second portion of the substrate; an inter-layer dielectric (ILD) over a portion of the substrate and on sidewalls of the first, second and third HKMG structures; a spacer liner on sidewalls of the ILD between the second and third HKMG structures; and a buried contact layer between the spacer liner and in a portion of the substrate.

## Claims

### Claim 1

A device comprising:
first and second high-k/metal gate (HKMG) structures over a first portion of a substrate, and a third HKMG structure over a second portion of the substrate;
an inter-layer dielectric (ILD) over a portion of the substrate and on sidewalls of the first, second and third HKMG structures;
a spacer liner on sidewalls of the ILD between the second and third HKMG structures; and
a buried contact layer between the spacer liner and in a portion of the substrate,
wherein the spacer liner comprises a top surface, a first surface and a second side surface, wherein the top surface of the spacer liner is in direct contact with the ILD, wherein a portion of the first surface of the spacer liner is in direct contact with the ILD, and wherein a portion of the second surface of the spacer liner is in direct contact with the buried contact layer, and
wherein the first, second and third HKMG structures comprise:
a high-k (HK) on sidewall portions of first, second and third fin structures;
a work function metal (WFM) layer over the HK layer;
a first spacer over the HK layer and the WFM layer and on sidewall portions of the first, second and third fin structures; and
a second spacer over the first spacer.

### Claim 2 (depends on 1)

The device according to claim 1, wherein the substrate is a silicon (Si) substrate, a portion of the Si substrate below the first and third HKMG structures comprises silicon-phosphorus (SiP), and wherein a portion of the Si substrate below the second HKMG structure comprises silicon germanium doped with boron (SiGe:B).

### Claim 3 (depends on 2)

The device according to claim 2, further comprising:
shallow trench isolation (STI) regions in a portion of the Si substrate;
a silicide layer in a portion of the Si substrate, between the STI regions, and adjacent to the first, second and third HKMG structures; and
a bottom spacer over the silicide layer and the STI regions.

### Claim 4 (depends on 1)

The device according to claim 1, further comprising:
a top source/drain (S/D) regions over the first, second and third HKMG structures and between the first spacer.

### Claim 5 (depends on 4)

The device according to claim 4, further comprising:
a second ILD over the buried contact layer and the spacer liner; and
a contact through the ILD to the top S/D regions layer, upper surface of the contact substantially coplanar to upper surface of the ILD.

### Claim 6 (depends on 1)

The device according to claim 1, wherein the spacer liner has a width of 4 nanometer (nm) to 10 nm.

### Claim 7 (depends on 1)

The device according to claim 1, wherein the buried contact layer has a thickness of 10 nanometer (nm) to 50 nm.

### Claim 8 (depends on 1)

The device according to claim 1, wherein the buried contact layer comprises a combination of thin layer of silicide at the bottom and fill metals.

### Claim 9

A device comprising:
first and second high-k/metal gate (HKMG) structures over a first portion of a silicon (Si) substrate, and a third HKMG structure over a second portion of the Si substrate;
an inter-layer dielectric (ILD) over a portion of the Si substrate and on sidewalls of the first, second and third HKMG structures;
a spacer liner on sidewalls of the ILD between the second and third HKMG structures; and
a buried contact layer between the spacer liner and in a portion of the Si substrate,
wherein the spacer liner comprises a top surface, a first surface and a second side surface, wherein the top surface of the spacer liner is in direct contact with the ILD, wherein a portion of the first surface of the spacer liner is in direct contact with the ILD, and wherein a portion of the second surface of the spacer liner is in direct contact with the buried contact layer, and
wherein the first, second and third HKMG structures comprise:
a high-k (HK) layer on sidewall portions of first, second and third fin structures;
a work function metal (WFM) layer over the HK layer;
a first spacer over the HK layer and the WFM layer and on sidewall portions of the first, second and third fin structures;
a second spacer over the first spacer; and
a top source/drain (S/D) regions over the first, second and third HKMG structures and between the first spacer.

### Claim 10 (depends on 9)

The device according to claim 9, further comprising:
shallow trench isolation (STI) regions in a portion of the Si substrate;
a silicide layer in a portion of the Si substrate, between the STI regions, and adjacent to the first, second and third HKMG structures; and
a bottom spacer over the silicide layer and the STI regions,
wherein a portion of the Si substrate below the first and third HKMG structures comprises silicon-phosphorus (SiP), and wherein a portion of the Si substrate below the second HKMG structure comprises silicon germanium doped with boron (SiGe:B).