# US 10,770,584 B2 · Drain extended transistor with trench gate

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- Number: US 10,770,584 B2
- Document ID: US10770584B2
- Status: Granted
- Kind: B2
- Application number: 16/185,679
- Filed: 2018-11-09
- Published: 2020-05-14
- Granted: 2020-09-08
- Earliest claimed: 2018-11-09
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Christopher Boguslaw Kocon
- Web page: https://patentgrep.com/patent/US10770584B2

## CPC

- H10D 30/658: {having trench gate electrodes}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0287: {using recessing of the source electrodes}
- H10D 30/0289: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/154: {Dispositions}
- H10D 62/158: {Dispositions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/025: {forming recessed gates, e.g. by using local oxidation}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10P 32/1406: {by ion implantation}
- H10P 32/171: {being group IV material}
- H10W 10/012: {using local oxidation of silicon [LOCOS]}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10D 30/0212: {using self-aligned silicidation}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate with a trench, a body region under the trench with majority carrier dopants of a first type, and a transistor, including a source region under the trench with majority carrier dopants of a second type, a drain region spaced from the trench with majority carrier dopants of the second type, a gate structure in the trench proximate a channel portion of a body region, and an oxide structure in the trench proximate a side of the gate structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate with a trench that extends inward from a side of the semiconductor substrate;
a body region under the trench in the semiconductor substrate, the body region including majority carrier dopants of a first type; and
a drain extended transistor, including:
a source region under the trench in the semiconductor substrate adjacent a channel portion of the body region, the source region including majority carrier dopants of a second type,
a drain region spaced from the trench in the semiconductor substrate, the drain region including majority carrier dopants of the second type,
a drift region between the channel portion of the body region and the drain region, the drift region including majority carrier dopants of the second type,
a gate structure, including: a gate dielectric layer in the trench proximate the channel portion of the body region, and a gate electrode on the gate dielectric layer in the trench, and
an oxide structure in the trench between a side of the gate structure and the drift region,
wherein the drain region is spaced from the gate structure by a first distance;
wherein the semiconductor substrate includes:
a second trench that extends inward from the side of the semiconductor substrate, and
a second body region under the second trench in the semiconductor substrate, the second body region including majority carrier dopants of the first type;
wherein the semiconductor device further comprises a second drain extended transistor, including:
a second source region under the second trench in the semiconductor substrate adjacent a second channel portion of the second body region, the second source region including majority carrier dopants of the second type,
a second drain region spaced from the second trench in the semiconductor substrate, the second drain region including majority carrier dopants of the second type,
a second drift region between the second channel portion of the second body region and the second drain region, the second drift region including majority carrier dopants of the second type,
a second gate structure, including: a second gate dielectric layer in the second trench proximate the second channel portion of the second body region, and a second gate electrode on the second gate dielectric layer in the second trench, and
a second oxide structure in the second trench between a side of the second gate structure and the second drift region;
wherein the second drain region is spaced from the second gate structure by a second distance; and
wherein the first distance is different than the second distance.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the trench has a first trench depth, wherein the second trench has a second trench depth, and wherein the first and second trench depths are the same.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the drift region and the second drift region have the same doping profile of the majority carrier dopants of the second type.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the drift region and the second drift region have the same doping profile of the majority carrier dopants of the second type.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the oxide structure and the second oxide structure are local oxidation of silicon (LOCOS) structures.

### Claim 6

A semiconductor device, comprising:
a semiconductor substrate with a trench that extends inward from a side of the semiconductor substrate, the trench having side surfaces and a bottom surface;
a body region under the trench in the semiconductor substrate, the body region including majority carrier dopants of a first type; and
a drain extended transistor, including:
a source region under the bottom surface of the trench in the semiconductor substrate adjacent a channel portion of the body region, the source region including majority carrier dopants of a second type, the channel portion under the bottom surface of the trench,
a drain region spaced from the trench in the semiconductor substrate, the drain region including majority carrier dopants of the second type,
a drift region between the channel portion of the body region and the drain region, the drift region including majority carrier dopants of the second type,
a gate structure, including: a gate dielectric layer in the trench proximate the channel portion of the body region, and a gate electrode on the gate dielectric layer in the trench, and
an oxide structure in the trench between a side of the gate structure and the drift region.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the oxide structure is a local oxidation of silicon (LOCOS) structure.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the semiconductor device is a discrete transistor device with a single transistor.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the semiconductor device is an integrated circuit with a plurality of transistors.

### Claim 10 (depends on 6)

The semiconductor device of claim 6, wherein the channel portion is a lateral channel.

### Claim 11 (depends on 6)

The semiconductor device of claim 6, further comprising a source contact structure extending through the trench and contacting the source region below the trench.

### Claim 12

A drain extended transistor, comprising:
a source region under a trench of a semiconductor substrate, the source region laterally adjacent a channel portion of a body region, the body region including majority carrier dopants of a first type, the source region including majority carrier dopants of a second type;
a drain region spaced from the trench in the semiconductor substrate, the drain region including majority carrier dopants of the second type;
a drift region between the channel portion of the body region and the drain region, the drift region including majority carrier dopants of the second type;
a gate structure, including: a gate dielectric layer in the trench proximate the channel portion of the body region, and a gate electrode on the gate dielectric layer in the trench; and
an oxide structure in the trench between a side of the gate structure and the drift region.

### Claim 13 (depends on 12)

The drain extended transistor of claim 12, wherein the oxide structure is a local oxidation of silicon (LOCOS) structure.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein the channel portion is a lateral channel.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, further comprising a source contact structure extending through the trench and contacting the source region below the trench.

### Claim 16

A semiconductor device, comprising:
a semiconductor substrate with a trench, the trench having side surfaces and a bottom surface;
a body region under the trench in the semiconductor substrate;
a drain extended transistor, including:
a source region laterally adjacent a channel portion of the body region at a location under the bottom surface of the trench,
a drain region spaced from the trench in the semiconductor substrate,
a drift region between the channel portion of the body region and the drain region,
a gate structure, including: a gate dielectric layer and a gate electrode in the trench over the channel portion of the body region, and
an oxide structure in the trench between a side of the gate structure and the drift region; and
a source contact structure extending through the trench and contacting the source region below the trench.