# US 10,770,575 B2 · Vertical group III-N devices and their methods of fabrication

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- Number: US 10,770,575 B2
- Document ID: US10770575B2
- Status: Granted
- Kind: B2
- Application number: 16/321,722
- Filed: 2016-09-30
- Published: 2020-02-27
- Granted: 2020-09-08
- Earliest claimed: 2016-09-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Sansaptak Dasgupta; Han Wui Then; Marko Radosavljevic; Pavel M. Agababov
- Web page: https://patentgrep.com/patent/US10770575B2

## CPC

- H10D 30/477: {Vertical HEMTs or vertical HHMTs}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Vertical Group III-N devices and their methods of fabrication are described. In an example, a semiconductor structure includes a doped buffer layer above a substrate, and a group III-nitride (III-N) semiconductor material disposed on the doped buffer layer, the group III-N semiconductor material having a sloped sidewall and a planar uppermost surface. A drain region is disposed adjacent to the doped buffer layer. An insulator layer is disposed on the drain region. A polarization charge inducing layer is disposed on and conformal with the group III-N semiconductor material, the polarization charge inducing layer having a first portion disposed on the sloped sidewall of the group III-N semiconductor material and a second portion disposed on the planar uppermost surface of the group III-N semiconductor material. A gate structure is disposed on the first portion of the polarization charge inducing layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a doped buffer layer above a substrate;
a group III-nitride (III-N) semiconductor material disposed on the doped buffer layer, the group III-N semiconductor material having a sloped sidewall and a planar uppermost surface;
a drain region disposed adjacent to the doped buffer layer;
an insulator layer disposed on the drain region;
a polarization charge inducing layer disposed on and conformal with the group III-N semiconductor material, the polarization charge inducing layer having a first portion disposed on the sloped sidewall of the group III-N semiconductor material and a second portion disposed on the planar uppermost surface of the group III-N semiconductor material, wherein the first portion has a thickness and the second portion has a thickness greater than the thickness of the first portion;
a gate structure disposed on the first portion of the polarization charge inducing layer; and
a source region disposed on the second portion of the polarization charge inducing layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, further comprising a highly n-doped semiconductor material between the second portion of the polarization charge inducing layer and the source region.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the first portion of the polarization charge inducing layer comprises a gate to drain separation portion disposed between the group III-N semiconductor material and the insulator layer and is in contact with the doped buffer layer.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the first portion of the polarization charge inducing layer is disposed on an uppermost surface of the insulator layer, and not between the group III-N semiconductor material and the insulator layer.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the group III-N semiconductor material includes gallium nitride (GaN), the polarization charge inducing layer includes a group III-N semiconductor material that includes aluminum.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the second portion of the polarization charge inducing layer disposed on the uppermost surface of the group III-N semiconductor material has a thickness that is at least 10 times greater than the first portion disposed on the sloped sidewalls of the group III-N semiconductor material.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the polarization charge inducing layer disposed on the sloped sidewalls and on the uppermost surface of the group III-N semiconductor material has a thickness in the range of 1 nm-3 nm and 10 nm-30 nm, respectively.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the gate structure comprises a gate electrode and a gate dielectric layer between the gate electrode and the polarization charge inducing layer, and the gate structure comprises one or more layers of a metal and a metal alloy.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the doped buffer layer includes n-type impurity dopants.

### Claim 10

A semiconductor structure, comprising:
a doped buffer layer above a substrate;
a group III-N semiconductor material disposed on the doped buffer layer, the group III-N semiconductor material having a pair of sloped sidewalls and a planar uppermost surface;
a first and a second drain region disposed on the substrate separated by the doped buffer layer;
an insulator layer disposed on the first and the second drain regions;
a polarization charge inducing layer disposed on and conformal with the group III-N semiconductor material, the polarization charge inducing layer having a first portion disposed on the sloped sidewalls of the group III-N semiconductor material and a second portion disposed on the planar uppermost surface of the group III-N semiconductor material, wherein the first portion has a thickness and the second portion has a thickness greater than the thickness of the first portion;
a first gate and a second gate structure disposed on the first portion of the polarization charge inducing layer, the first and the second gate structures separated by the group III-N semiconductor material; and
a source region disposed on the second portion of the polarization charge inducing layer.

### Claim 11 (depends on 10)

The semiconductor structure of claim 10, further comprising a highly n-doped semiconductor material between the second portion of the polarization charge inducing layer and the source region.

### Claim 12 (depends on 10)

The semiconductor structure of claim 10, wherein the first portion of the polarization charge inducing layer comprises a gate extension portion disposed between the group III-N semiconductor material and the insulator layer and is in contact with the doped buffer layer.

### Claim 13 (depends on 10)

The semiconductor structure of claim 10, wherein the first portion of the polarization charge inducing layer is disposed on an uppermost surface of the insulator layer, and not between the group III-N semiconductor material and the insulator layer.

### Claim 14 (depends on 10)

The semiconductor structure of claim 10, wherein the group III-N semiconductor material includes gallium nitride (GaN) and the polarization charge inducing layer includes a group III-N semiconductor material that includes aluminum.

### Claim 15 (depends on 10)

The semiconductor structure of claim 10, wherein the portion of the polarization charge inducing layer disposed on the uppermost surface of the group III-N semiconductor material has a thickness that is at least 10 times greater than the portion disposed on the sloped sidewalls of the group III-N semiconductor material.

### Claim 16 (depends on 10)

The semiconductor structure of claim 10, wherein the polarization charge inducing layer disposed on the sloped sidewalls and on the uppermost surface of the group III-N semiconductor material has a thickness in the range of 1 nm-3 nm and 10 nm-30 nm, respectively.

### Claim 17 (depends on 10)

The semiconductor structure of claim 10, wherein the gate structure comprises a gate electrode and a gate dielectric layer between the gate electrode and the polarization charge inducing layer, and the gate structure comprises one or more layers of a metal and a metal alloy.

### Claim 18 (depends on 10)

The semiconductor structure of claim 10, wherein the doped buffer layer includes n-type impurity dopants.

### Claim 19

A method of fabricating a group III-nitride (III-N) transistor, the method comprising:
forming a material layer stack on a substrate, the material layer stack comprising a metal layer and an insulator layer on the metal layer;
forming a trench in the material layer stack;
forming a doped buffer layer in the trench;
forming a group III-N semiconductor material in the trench and on the doped buffer layer, wherein the group III-N material has sidewalls and an uppermost surface;
forming a polarization charge inducing layer on the sidewalls and on the uppermost surface of the group III-N semiconductor material;
where the portion of the polarization charge inducing layer formed on the sidewall of the group III-N semiconductor material has a thickness less than a thickness of the portion of the polarization charge inducing layer on the uppermost surface of the group III-N semiconductor material;
forming a dielectric hardmask layer on an uppermost surface of the polarization charge inducing layer and on a portion of a sidewall surface of the polarization charge inducing layer;
forming a gate stack on the polarization charge inducing layer on the sidewall of the polarization charge inducing layer, and on the hardmask layer;
forming a dielectric layer on the gate stack, on the insulator layer planarizing to expose the hardmask layer;
forming a source contact on an uppermost surface of the polarization charge inducing layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein forming the group III-N semiconductor material comprises leaving an exposed portion of the uppermost surface of the doped buffer layer.

### Claim 21 (depends on 19)

The method of claim 19, wherein forming the polarization charge inducing layer comprises forming the polarization charge inducing layer on a portion of an uppermost surface of the doped buffer layer and on the group III-N semiconductor material.

### Claim 22 (depends on 19)

The method of claim 19, wherein thinning the polarization charge inducing layer further comprises forming the dielectric hardmask layer and performing an isotropic plasma etch.

### Claim 23 (depends on 19)

The method of claim 19, wherein the method further comprises forming a highly n-doped material above the uppermost surface of the polarization charge inducing layer.