# US 10,770,574 B2 · Semiconductor device and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,574 B2 - Document ID: US10770574B2 - Status: Granted - Kind: B2 - Application number: 16/463,742 - Filed: 2018-10-16 - Published: 2019-12-19 - Granted: 2020-09-08 - Earliest claimed: 2017-10-16 - Assignees: Dynax Semiconductor, Inc. - Applicants: Dynax Semiconductor, Inc. - Inventors: Naiqian Zhang; Xingxing Wu; Xinchuan Zhang - Web page: https://patentgrep.com/patent/US10770574B2 ## CPC - H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] - H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts} - H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT} - H10D 30/471: {High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]} - H10D 30/87: FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] {(FETs having Schottky contact on top of heterojunction gate H10D30/801)} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes an active region and an inactive region located outside of the active region, the semiconductor device including a substrate, a semiconductor layer including a first semiconductor layer located in the active region and a second semiconductor layer located in the inactive region, a source, a drain, and a gate. A via hole penetrated through the substrate and the semiconductor layers below the source is provided below the source. A part of the via hole is located in the second semiconductor layer of the inactive region and penetrates at least one part of the second semiconductor layer. ## Claims ### Claim 1 A semiconductor device, wherein the semiconductor device comprises an active region and an inactive region located outside of the active region, the semiconductor device comprising: a substrate; a semiconductor layer formed at a side of the substrate, the semiconductor layer comprising a first semiconductor layer located in the active region and a second semiconductor layer located in the inactive region; a source, a drain, and a gate formed in the active region and located at a side of the semiconductor layer away from the substrate, the second semiconductor layer located in the inactive region close to at least one end of the source; and a via hole penetrated through the substrate, at least a part of the first semiconductor layer, and at least a part of the second semiconductor layer. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein a projection of the via hole on a plane of the substrate partially overlaps a projection of the source on the plane of the substrate. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein one of i) the source is formed on a surface at a side of the semiconductor device away from the substrate, and ii) a recess for accommodating the source is disposed at a side of the semiconductor layer away from the substrate, the source located in the recess. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, wherein each of two ends of the source is provided with one said via hole, and a distance between two said via holes provided at two end edges of the source is greater than or equal to a quarter of a width of the gate. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein at least one end of the source is disposed as a concave structure, and wherein a projection of the via hole on a plane of the substrate does not overlap or partially overlaps a projection of the source on the plane of the substrate. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein one of i) the source is formed on a surface at a side of the semiconductor device away from the substrate, and ii) a recess for accommodating the source is disposed at a side of the semiconductor layer away from the substrate, the source located in the recess. ### Claim 7 (depends on 5) The semiconductor device according to claim 5, wherein each of two ends of the source is provided with one said via hole, and a distance between two said via holes provided at two end edges of the source is greater than or equal to a quarter of a width of the gate. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein an interconnecting metal layer is disposed on a surface of the source and the second semiconductor layer away from the substrate. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the second semiconductor layer is a portion of the semiconductor layer in a region where the interconnecting metal layer and the inactive region overlap. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein a barrier layer is disposed at a side of the first semiconductor layer and the second semiconductor layer away from the substrate at a position corresponding to the via hole. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein an interconnecting metal layer is disposed on a surface at a side of the source, the second semiconductor layer, and the barrier layer away from the substrate. ### Claim 12 (depends on 10) The semiconductor device according to claim 10, wherein one of i) the source is formed on a surface at a side of the semiconductor device away from the substrate, and ii) a recess for accommodating the source is disposed at a side of the semiconductor layer away from the substrate, the source located in the recess. ### Claim 13 (depends on 10) The semiconductor device according to claim 10, wherein each of two ends of the source is provided with one said via hole, and a distance between two said via holes provided at two end edges of the source is greater than or equal to a quarter of a width of the gate. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein one of i) the source is formed on a surface at a side of the semiconductor device away from the substrate, and ii) a recess for accommodating the source is disposed at a side of the semiconductor layer away from the substrate, the source located in the recess. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein the source is formed in the recess, and wherein a height difference between a bottom surface of the via hole located in the second semiconductor layer and a surface of the semiconductor layer away from the substrate is smaller than or equal to 250 nm. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, wherein each of two ends of the source is provided with one said via hole, and wherein a distance between two said via holes provided at two end edges of the source is greater than or equal to a quarter of a width of the gate. ### Claim 17 (depends on 1) The semiconductor device according to claim 1, wherein one-sixth to five-sixths of the volume of the via hole is located in the second semiconductor layer. ### Claim 18 (depends on 1) The semiconductor device according to claim 1, wherein an edge of the second semiconductor layer is arc-shaped. ### Claim 19 A method for manufacturing a semiconductor device, the method comprising: providing a substrate; forming semiconductor layers at a side of the substrate to form an active region and an inactive region, the semiconductor layers comprising a first semiconductor layer located in the active region and a second semiconductor layer located in the inactive region; forming a source, a drain, and a gate in the active region, at a side of the semiconductor layer away from the substrate; forming an interconnecting metal at a side of the source away from the semiconductor layer and a side of the second semiconductor layer away from the substrate; and forming a via hole penetrated through the substrate, at least a part of the first semiconductor layer, and at least a part of the second semiconductor layer from a side of the substrate away from the semiconductor layers. ### Claim 20 (depends on 19) The method for manufacturing a semiconductor device according to claim 19, wherein the method further comprises: prior to forming the interconnecting metal, forming an etching stopping layer at a side of the semiconductor layers away from the substrate, the etching stopping layer located above the via hole.