# US 10,770,573 B2 · Apparatus, system and method of an electrostatically formed nanowire (EFN)

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- Number: US 10,770,573 B2
- Document ID: US10770573B2
- Status: Granted
- Kind: B2
- Application number: 16/136,714
- Filed: 2018-09-20
- Published: 2020-03-26
- Granted: 2020-09-08
- Earliest claimed: 2018-09-20
- Assignees: Tower Semiconductor Ltd.; Ramot at Tel-Aviv University Ltd.
- Applicants: Tower Semiconductor Ltd.; RAMOT at Tel Aviv University Ltd.
- Inventors: Zohar Shaked; Yakov Roizin; Menachem Vofsy; Alexey Heiman; Yossi Rosenwaks; Klimentiy Shimanovich; Yhonatan Vaknin
- Web page: https://patentgrep.com/patent/US10770573B2

## CPC

- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6758: {characterised by the insulating substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 15/00: Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
- G01N 27/4141: {specially adapted for gases}
- G01N 27/4146: {involving nanosized elements, e.g. nanotubes, nanowires}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 62/221: {of FETs}
- H10D 64/411: {for FETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q)

## Abstract

For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

## Claims

### Claim 1

An Electrostatically Formed Nanowire (EFN) comprising:
a source region;
at least one drain region;
a wire region configured to drive a current between the source and drain regions via a conductive channel;
a first lateral-gate area extending along a first surface of the wire region between said source and drain regions;
a second lateral-gate area extending along a second surface of the wire region between said source and drain regions; and
a sensing area in an opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

### Claim 2 (depends on 1)

The EFN of claim 1 comprising at least first and second drain regions, the wire region configured to, based on a first voltage at the first lateral-gate area and a second voltage at the second lateral-gate area, drive the current between the source region and the first drain region or the second drain region.

### Claim 3 (depends on 1)

The EFN of claim 1, wherein the sensing area is in a Buried Oxide (BOX) layer of the silicon substrate.

### Claim 4 (depends on 1)

The EFN of claim 1, wherein the sensing area comprises a dielectric layer in contact with the first and second lateral-gate areas and the wire region.

### Claim 5 (depends on 1)

The EFN of claim 1 comprising a top-gate area over a third surface of said wire region.

### Claim 6 (depends on 5)

The EFN of claim 5, wherein the top-gate area is operable to control a vertical size of a depletion region in the wire region.

### Claim 7 (depends on 1)

The EFN of claim 1 comprising a functional layer at the backside of the silicon substrate and in contact with the sensing area, the functional layer configured to react with the predefined substance.

### Claim 8 (depends on 7)

The EFN of claim 7, wherein the functional layer is operable as a backside-gate to control a vertical size of a depletion region in the wire region.

### Claim 9 (depends on 1)

The EFN of claim 1, wherein the predefined substance comprises a gas.

### Claim 10 (depends on 1)

The EFN of claim 1 comprising a heater configured to heat the wire region.

### Claim 11 (depends on 1)

The EFN of claim 1, wherein the first and second lateral-gate areas are operable to control a lateral size of a depletion region in the wire region.

### Claim 12 (depends on 1)

The EFN of claim 1, wherein the drain region is reflectionally symmetric to the source region, and the first lateral-gate area is reflectionally symmetric to the second lateral-gate area.

### Claim 13 (depends on 1)

The EFN of claim 1, wherein the drain region is aligned with the source region, and the second lateral-gate area is aligned with the first lateral-gate area.

### Claim 14 (depends on 1)

The EFN of claim 1, wherein the source and drain regions comprise heavily doped N-type silicon, and the first and second lateral-gate areas comprise heavily doped P-type silicon.

### Claim 15

A gas sensor configures to sense at least one predefined type of gas, the gas sensor comprising:
at least one Electrostatically Formed Nanowire (EFN) comprising:
a source region;
at least one drain region;
a wire region configured to drive a current between the source and drain regions via a conductive channel;
a first lateral-gate area extending along a first surface of the wire region between said source and drain regions;
a second lateral-gate area extending along a second surface of the wire region between said source and drain regions; and
a sensing area in an opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined gas, cause a change in a conductivity of the conductive channel; and
a detector to detect the predefined gas based on the current via the conductive channel.

### Claim 16 (depends on 15)

The gas sensor of claim 15 comprising two or more EFNs configured to sense two or more respective predefined types of gas.