# US 10,770,572 B2 · Lateral insulated-gate bipolar transistor and manufacturing method therefor

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- Number: US 10,770,572 B2
- Document ID: US10770572B2
- Status: Granted
- Kind: B2
- Application number: 16/311,276
- Filed: 2017-06-21
- Published: 2019-08-08
- Granted: 2020-09-08
- Earliest claimed: 2016-06-21
- Assignees: Csmc Technologies Fab2 Co., Ltd.
- Applicants: Csmc Technologies Fab2 Co., Ltd.
- Inventors: Shukun Qi
- Web page: https://patentgrep.com/patent/US10770572B2

## CPC

- H10D 12/411: {Insulated-gate bipolar transistors [IGBT]}
- H10D 12/00: Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D 12/031: {of IGBTs}
- H10D 12/421: {on insulating layers or insulating substrates, e.g. thin-film IGBTs}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/231: {Emitter or collector electrodes for bipolar transistors}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A lateral insulated-gate bipolar transistor and a manufacturing method therefor. The lateral insulated-gate bipolar transistor comprises a substrate, an anode terminal and a cathode terminal on the substrate, and a drift region and a gate electrode located between the anode terminal and the cathode terminal. The anode terminal comprises an N-shaped buffer zone on the substrate, a P well in the N-shaped buffer zone, an N+ zone in the P well, a groove located above the N+ zone and partially encircled by the P well, polycrystalline silicon in the groove, P+ junctions at two sides of the groove, and N+ junctions at two sides of the P+ junctions.

## Claims

### Claim 1

A lateral insulated-gate bipolar transistor, comprising:
a P-type substrate;
a cathode terminal located on the substrate;
an anode terminal located on the substrate, the anode terminal comprising an N-type buffer region located on the substrate, a P well located in the N-type buffer region, an N+ region located in the P well, a trench located above the N+ region and partially surrounded by the P well, a polysilicon located in the trench, P+ junctions located at both sides of the trench, and N+ junctions located at both sides of the P+ junction;
a drift region located between the anode terminal and the cathode terminal; and
a gate located between the anode terminal and the cathode terminal;
wherein the trench is a structure gradually increased in width from bottom to top to form a slope and having a narrow bottom and a wide top.

### Claim 2 (depends on 1)

The lateral insulated-gate bipolar transistor according to claim 1, wherein a dopant concentration of the N-type buffer region is less than a dopant concentration of the P well, and the dopant concentration of the P well is less than dopant concentrations of the P+ junction and the N+ junction.

### Claim 3 (depends on 2)

The lateral insulated-gate bipolar transistor according to claim 2, wherein the dopant concentration of the N-type buffer region ranges from 2E15 to 5E15 cm−3, the dopant concentration of the P well ranges from 4E17 to 8E17 cm−3, and the dopant concentrations of the P+ junction and the N+ junction range from 5E20 to 10E20 cm−3.

### Claim 4 (depends on 1)

The lateral insulated-gate bipolar transistor according to claim 1, wherein the anode terminal further comprises an oxide layer located on an inner surface of the trench, the oxide layer comprises an oxide film located on a sidewall of the trench and a spacer structure located at both sides of a bottom of the trench, the oxide layer has a void at a position corresponding to a middle portion of the bottom of the trench, such that the polysilicon is in direct contact with the N+ region below.

### Claim 5 (depends on 1)

The lateral insulated-gate bipolar transistor according to claim 1, wherein a dopant concentration of the polysilicon ranges from 1E21 to 10E22 cm−3.

### Claim 6 (depends on 1)

The lateral insulated-gate bipolar transistor according to claim 1, wherein the lateral insulated-gate bipolar transistor is a silicon-on-insulator type lateral insulated-gate bipolar transistor; the lateral insulated-gate bipolar transistor further comprises a buried oxide layer located between the substrate and the drift region; the substrate is a P-type substrate, and the drift region is an N-type drift region.

### Claim 7 (depends on 1)

The lateral insulated-gate bipolar transistor according to claim 1, wherein the P-well extends into contact with the P+ junctions.

### Claim 8 (depends on 1)

The lateral insulated-gate bipolar transistor according to claim 1, wherein the P-well and the P+ junctions separate the trench from the N-type buffer region.