# US 10,770,570 B2 · FinFET device and methods of forming

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,770,570 B2
- Document ID: US10770570B2
- Status: Granted
- Kind: B2
- Application number: 16/173,642
- Filed: 2018-10-29
- Published: 2019-02-28
- Granted: 2020-09-08
- Earliest claimed: 2016-11-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yu-Chang Lin; Chun-Feng Nieh; Huicheng Chang; Wei-Ting Chien; Chih-Pin Tsao; Hou-Ju Li; Tien-Shun Chang
- Web page: https://patentgrep.com/patent/US10770570B2

## CPC

- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 30/022: {having lightly-doped source or drain extensions selectively formed at the sides of the gates}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 84/853: {comprising FinFETs}
- H10P 32/1408: {from or through or into an external applied layer, e.g. photoresist or nitride layers}
- H10P 32/171: {being group IV material}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.

## Claims

### Claim 1

A fin field effect transistor (finFET) device comprising:
a fin extending upwards from a semiconductor substrate;
a gate stack over and along sidewalls of a channel region of the fin;
a source/drain region adjacent the fin;
a gate spacer disposed along a sidewall of the gate stack;
a first carbon-doped region disposed along a bottom surface and a sidewall of the source/drain region, wherein the first carbon-doped region is between the sidewall of the source/drain region and the channel region along a line parallel to a major surface of the semiconductor substrate; and
a second carbon-doped region under the gate spacer and between the first carbon-doped region and the channel region, wherein the first carbon-doped region and the second carbon-doped region have different concentrations of carbon.

### Claim 2 (depends on 1)

The finFET device of claim 1, wherein the second carbon-doped region is disposed in a lightly-doped drain (LDD) region of the finFET device.

### Claim 3 (depends on 1)

The finFET device of claim 1, wherein the gate spacer comprises carbon dopants.

### Claim 4 (depends on 1)

The finFET device of claim 1, wherein the second carbon-doped region has a lower concentration of carbon than the first carbon-doped region.

### Claim 5 (depends on 4)

The finFET device of claim 4, wherein a carbon concentration of the first carbon-doped region is 3×1020 cm−3 or greater, and wherein a carbon concentration of the second carbon-doped region is in the range of 1×1019 cm−3 to 5×101 cm−3.

### Claim 6 (depends on 1)

The finFET device of claim 1, wherein a ratio of a carbon concentration of the first carbon-doped region at a top of the fin to carbon concentrations of the first carbon-doped region at a sidewall of the fin to a carbon concentration of the first carbon-doped region at a bottom of the fin is in the range of 1:0.65:0.65 to 1:0.9:0.9.

### Claim 7 (depends on 1)

The finFET device of claim 1, wherein the first carbon-doped region extends lower than the second carbon-doped region.

### Claim 8 (depends on 1)

The finFET device of claim 1, wherein a carbon concentration of the first carbon-doped region increases in a direction towards the source/drain region.

### Claim 9

A fin field effect transistor (finFET) device comprising:
a semiconductor fin disposed between isolation regions;
a gate stack over and along sidewalls of a channel region of the semiconductor fin, wherein the channel region is doped with carbon;
a source/drain region adjacent the semiconductor fin;
a carbon-doped gate spacer disposed along a sidewall of the gate stack;
a carbon film over the carbon-doped gate spacer, wherein the carbon film extends along the sidewall of the gate stack; and
a first carbon-doped region under the carbon-doped gate spacer.

### Claim 10 (depends on 9)

The finFET device of claim 9 further comprising a second carbon-doped region disposed along sidewalls and a bottom surface of the source/drain region.

### Claim 11 (depends on 10)

The finFET device of claim 10, wherein the second carbon-doped region is disposed between at least a portion of the source/drain region and the first carbon-doped region.

### Claim 12 (depends on 10)

The finFET device of claim 10, wherein the first carbon-doped region has a lower concentration of carbon than the second carbon-doped region.

### Claim 13 (depends on 10)

The finFET device of claim 10, wherein the second carbon-doped region extends under the carbon-doped gate spacer.

### Claim 14 (depends on 9)

The finFET device of claim 9 further comprising one or more additional gate spacers over the carbon film, wherein the one or more additional gate spacers extend along the sidewall of the gate stack.

### Claim 15

A fin field effect transistor (finFET) device comprising:
a semiconductor fin extending from a semiconductor substrate;
a gate stack over and along sidewalls of the semiconductor fin;
a carbon-comprising gate spacer disposed along a sidewall of the gate stack;
a lightly doped drain (LDD) region under the carbon-comprising gate spacer, wherein the LDD region comprises carbon;
an epitaxial source/drain region adjacent the LDD region; and
carbon-doped semiconductor liner disposed along sidewalls and a bottom surface of the epitaxial source/drain region, wherein the carbon-doped semiconductor liner is disposed between the LDD region and a sidewall of the epitaxial source/drain region along a line parallel to a major surface of the semiconductor substrate, the carbon-doped semiconductor liner having a different concentration of carbon than the LDD region.

### Claim 16 (depends on 15)

The finFET device of claim 15, wherein the epitaxial source/drain region and the carbon-doped semiconductor liner extends under the carbon-comprising gate spacer.

### Claim 17 (depends on 15)

The finFET device of claim 15, wherein the carbon-doped semiconductor liner has a carbon concentration of 3×1020 cm−3 or greater.

### Claim 18 (depends on 15)

The finFET device of claim 15, wherein the LDD region has a carbon concentration in the range of 1×1019 cm−3 to 5×101 cm−3.

### Claim 19 (depends on 15)

The finFET device of claim 15, wherein a channel region of the semiconductor fin comprises carbon.

### Claim 20 (depends on 15)

The finFET device of claim 15, wherein an interface between the carbon-doped semiconductor liner and the epitaxial source/drain region is disposed directly under the carbon-comprising gate spacer.