# US 10,770,565 B2 · Memory structure and manufacturing method thereof

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- Number: US 10,770,565 B2
- Document ID: US10770565B2
- Status: Granted
- Kind: B2
- Application number: 16/123,868
- Filed: 2018-09-06
- Published: 2020-03-12
- Granted: 2020-09-08
- Earliest claimed: 2018-09-06
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Hsueh-Chun Hsiao; Tzu-Yun Chang; Chuan-Fu Wang; Yu-Huang Yeh
- Web page: https://patentgrep.com/patent/US10770565B2

## CPC

- H10D 30/0212: {using self-aligned silicidation}
- H10D 64/037: {comprising charge-trapping insulators}
- H10B 43/30: characterised by the memory core region
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/68: Floating-gate IGFETs
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/66: Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.

## Claims

### Claim 1

A memory structure, comprising:
a substrate;
a first gate structure comprising:
a first gate disposed on the substrate; and
a charge storage layer disposed between the first gate and the substrate;
a second gate structure disposed on the substrate at one side of the first gate structure, wherein the second gate structure comprises a second gate, and a height of the first gate is higher than a height of the second gate;
a first spacer and a second spacer respectively disposed on one sidewall and the other sidewall of the first gate structure, wherein the first spacer is located between the first gate structure and the second gate structure; and
a third spacer disposed on a sidewall of the first spacer and covering a portion of a top surface of the second gate, wherein
a top surface of the charge storage layer is lower than the entire top surface of the second gate, and
the first spacer covers a sidewall of the charge storage layer.

### Claim 2 (depends on 1)

The memory structure according to claim 1, wherein a height of the first spacer is higher than the height of the second gate, and the portion of the top surface of the second gate covered by the third spacer is parallel to a top surface of the substrate.

### Claim 3 (depends on 1)

The memory structure according to claim 1, wherein the first gate structure further comprises:
a first dielectric layer disposed between the charge storage layer and the substrate; and
a second dielectric layer disposed between the first gate and the charge storage layer.

### Claim 4 (depends on 1)

The memory structure according to claim 1, wherein the second gate structure further comprises:
a third dielectric layer disposed between the second gate and the substrate.

### Claim 5 (depends on 1)

The memory structure according to claim 1, further comprising:
a fourth spacer disposed on a sidewall of the second gate away from the first gate structure.

### Claim 6 (depends on 1)

The memory structure according to claim 1, further comprising:
a fifth spacer disposed on the second spacer.

### Claim 7 (depends on 1)

The memory structure according to claim 1, further comprising:
a sixth spacer disposed on the third spacer.

### Claim 8 (depends on 1)

The memory structure according to claim 1, further comprising:
a first metal silicide layer disposed on the first gate;
a second metal silicide layer disposed on the top surface of the second gate exposed by the third spacer;
a third metal silicide layer disposed on the substrate at one side of the first gate structure; and
a fourth metal silicide layer disposed on the substrate at the other side of the first gate structure.

### Claim 9

A method of manufacturing a memory structure, comprising:
forming a first gate structure on a substrate, wherein the first gate structure comprises:
a first gate disposed on the substrate; and
a charge storage layer disposed between the first gate and the substrate;
forming a second gate structure on the substrate at one side of the first gate structure, wherein the second gate structure comprises a second gate, and a height of the first gate is higher than a height of the second gate;
forming a first spacer and a second spacer respectively on one sidewall and the other sidewall of the first gate structure, wherein the first spacer is located between the first gate structure and the second gate structure; and
forming a third spacer on a sidewall of the first spacer, wherein the third spacer covers a portion of a top surface of the second gate, a top surface of the charge storage layer is lower than the entire top surface of the second gate, and the first spacer covers a sidewall of the charge storage layer.

### Claim 10 (depends on 9)

The method of manufacturing the memory structure according to claim 9, wherein a height of the first spacer is higher than the height of the second gate.

### Claim 11 (depends on 9)

The method of manufacturing the memory structure according to claim 9, further comprising:
forming a fourth spacer on a sidewall of the second gate away from the first gate structure.

### Claim 12 (depends on 9)

The method of manufacturing the memory structure according to claim 9, further comprising:
forming a fifth spacer on the second spacer.

### Claim 13 (depends on 9)

The method of manufacturing the memory structure according to claim 9, further comprising:
forming a sixth spacer on the third spacer.

### Claim 14 (depends on 9)

The method of manufacturing the memory structure according to claim 9, wherein a method of forming the third spacer comprising:
forming a second gate material layer covering the first gate structure;
removing a portion of the second gate material layer until a top surface of the second gate material layer is lower than a top surface of the first gate;
conformally forming a spacer material layer on the first gate structure and the second gate material layer;
performing an etch-back process on the spacer material layer to form the third spacer on the first spacer and a seventh spacer on the second spacer; and
removing the seventh spacer.

### Claim 15 (depends on 14)

The method of manufacturing the memory structure according to claim 14, wherein a method of removing the portion of the second gate material layer comprises an etch-back method or a combination of a chemical mechanical polishing method and the etch-back method.

### Claim 16 (depends on 14)

The method of manufacturing the memory structure according to claim 14, wherein a method of forming the second gate comprising:
patterning the second gate material layer.

### Claim 17 (depends on 9)

The method of manufacturing the memory structure according to claim 9, wherein the first gate structure further comprises:
a first dielectric layer disposed between the charge storage layer and the substrate; and
a second dielectric layer disposed between the first gate and the charge storage layer.

### Claim 18 (depends on 9)

The method of manufacturing the memory structure according to claim 9, wherein the first gate structure further comprises:
a cap layer disposed on the first gate.

### Claim 19 (depends on 18)

The method of manufacturing the memory structure according to claim 18, further comprising:
forming a first metal silicide layer on the first gate, wherein the cap layer is removed before the first metal silicide layer is formed;
forming a second metal silicide layer on the top surface of the second gate exposed by the third spacer;
forming a third metal silicide layer on the substrate at one side of the first gate structure; and
forming a fourth metal silicide layer on the substrate at the other side of the first gate structure.

### Claim 20 (depends on 9)

The method of manufacturing the memory structure according to claim 9, wherein the second gate structure further comprises:
a third dielectric layer disposed between the second gate and the substrate.