# US 10,770,563 B2 · Gate structure and patterning method for multiple threshold voltages > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,770,563 B2 - Document ID: US10770563B2 - Status: Granted - Kind: B2 - Application number: 16/363,109 - Filed: 2019-03-25 - Published: 2020-04-30 - Granted: 2020-09-08 - Earliest claimed: 2018-10-24 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Chung-Liang Cheng; Ziwei Fang - Web page: https://patentgrep.com/patent/US10770563B2 ## CPC - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections} - H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN} - H10D 64/685: {being perpendicular to the channel plane} - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10D 84/0177: {the gate conductors having different materials or different implants} - H10D 84/0181: {Manufacturing their gate insulating layers} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/8311: {the IGFETs characterised by having different channel structures} - H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties} - H10D 84/834: {comprising FinFETs} - H10D 84/853: {comprising FinFETs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor substrate; a plurality of fins disposed over the semiconductor substrate, the plurality of fins comprising a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions; and a plurality of gate structures comprising: an interfacial layer (IL) disposed over the plurality of channel regions; a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region; a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions, wherein the first, second and third high-k dielectric layers are different from one another. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first high-k dielectric layer has a first thickness, the second high-k dielectric layer has a second thickness, and the third high-k dielectric layer has a third thickness, wherein the third thickness is greater than the second thickness and the second thickness is greater than the first thickness. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the first high-k dielectric layer comprises aluminum, wherein the third high-k dielectric layer comprises lanthanum. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein, over the first p-type channel region and the first n-type channel region, the second high-k dielectric layer is disposed between the first high-k dielectric layer and the third high-k dielectric layer, wherein, over the third n-type channel region and the third p-type channel region, the third high-k dielectric layer is in contact with the interfacial layer. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the plurality of gate structures further comprises: a capping layer disposed over the third high-k dielectric layer over the plurality of channel regions; a barrier layer disposed over the capping layer over the plurality of channel regions; an n-type work function layer disposed over the capping layer over the plurality of channel regions; and over the first, second and third p-type channel regions, a p-type work function layer disposed between the n-type work function layer and the barrier layer. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the capping layer comprises titanium, silicon and nitrogen, wherein the barrier layer comprises tantalum and nitrogen. ### Claim 7 (depends on 5) The semiconductor device of claim 5, further comprising: a glue layer directly on the n-type work function layer over the plurality of channel regions; and a fill metal material over the glue layer. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the first n-type channel region comprises a first threshold voltage, the second n-type channel region comprises a second threshold voltage, and the third n-type channel region comprises a third threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage and the second threshold voltage is greater than the third threshold voltage. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the first p-type channel region comprises a fourth threshold voltage, the second p-type channel region comprises a fifth threshold voltage, and the third p-type channel region comprises a sixth threshold voltage, wherein the sixth threshold voltage is greater than the fifth threshold voltage and the fifth threshold voltage is greater than the fourth threshold voltage. ### Claim 10 A semiconductor device, comprising: a semiconductor substrate; a plurality of fins disposed over the semiconductor substrate, the plurality of fins comprising a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions; and a plurality of gate structures comprising: an interfacial layer (IL) disposed over the plurality of channel regions; a first high-k (HK) dielectric layer disposed on the interfacial layer over the first n-type channel region and the first p-type channel region; a second high-k dielectric layer disposed on the first high-k dielectric layer disposed over the first n-type channel region and the first p-type channel region, and on the interfacial layer disposed over the second n-type channel region and the second p-type channel region; and a third high-k dielectric layer disposed on the second high-k dielectric layer disposed over the first n-type channel region, the first p-type channel region, the second n-type channel region, the second p-type channel region, and on the interfacial layer disposed over the third n-type channel region and the third p-type channel region, wherein the first, second and third high-k dielectric layers are different from one another. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the first high-k dielectric layer has a first thickness, the second high-k dielectric layer has a second thickness, and the third high-k dielectric layer has a third thickness, wherein the third thickness is greater than the second thickness and the second thickness is greater than the first thickness. ### Claim 12 (depends on 10) The semiconductor device of claim 10, wherein the first high-k dielectric layer comprises aluminum, wherein the third high-k dielectric layer comprises lanthanum. ### Claim 13 (depends on 10) The semiconductor device of claim 10, wherein the plurality of gate structures further comprises: a capping layer disposed over the third high-k dielectric layer over the plurality of channel regions; a barrier layer disposed over the capping layer over the plurality of channel regions; an n-type work function layer disposed over the capping layer over the plurality of channel regions; and over the first, second and third p-type channel regions, a p-type work function layer disposed between the n-type work function layer and the barrier layer, wherein the capping layer comprises titanium, silicon and nitrogen, wherein the barrier layer comprises tantalum and nitrogen. ### Claim 14 (depends on 10) The semiconductor device of claim 10, wherein the first n-type channel region comprises a first threshold voltage, the second n-type channel region comprises a second threshold voltage, and the third n-type channel region comprises a third threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage and the second threshold voltage is greater than the third threshold voltage. ### Claim 15 (depends on 10) The semiconductor device of claim 10, wherein the first p-type channel region comprises a fourth threshold voltage, the second p-type channel region comprises a fifth threshold voltage, and the third p-type channel region comprises a sixth threshold voltage, wherein the sixth threshold voltage is greater than the fifth threshold voltage and the fifth threshold voltage is greater than the fourth threshold voltage. ### Claim 16 A semiconductor device, comprising: a first gate structure over a first fin, the first gate structure comprising: an interfacial layer over a channel region of the first fin, a first high-k dielectric layer on the interfacial layer, a second high-k dielectric layer on the first high-k dielectric layer, a third high-k dielectric layer on the second high-k dielectric layer, and a capping layer on the third high-k dielectric layer; a second gate structure over a second fin, the second gate structure comprising: the interfacial layer over a channel region of the second fin, the second high-k dielectric layer on the interfacial layer, the third high-k dielectric layer on the second high-k dielectric layer, and a capping layer on the third high-k dielectric layer; and a third gate structure over a third fin, the third gate structure comprising: the interfacial layer over a channel region of the third fin, the third high-k dielectric layer on the interfacial layer, and a capping layer on the third high-k dielectric layer, wherein the first high-k dielectric layer is doped with aluminum, wherein the third high-k dielectric layer is doped with lanthanum. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein the first high-k dielectric layer, the second high-k dielectric layer, and the third high-k dielectric layer comprise hafnium oxide. ### Claim 18 (depends on 16) The semiconductor device of claim 16, wherein the first high-k dielectric layer has a first thickness, the second high-k dielectric layer has a second thickness, and the third high-k dielectric layer has a third thickness, wherein the third thickness is greater than the second thickness and the second thickness is greater than the first thickness. ### Claim 19 (depends on 16) The semiconductor device of claim 16, wherein each of the first gate structure, the second gate structure, and the third gate structure further comprises: a barrier layer over the capping layer, an n-type work function layer over the barrier layer, a glue layer over the n-type work function layer, and a gate metal fill layer over the glue layer, wherein the capping layer comprises titanium silicide doped with nitrogen or titanium silicide and the barrier layer comprises tantalum nitride. ### Claim 20 (depends on 19) The semiconductor device of claim 19, wherein each of the first gate structure, the second gate structure, and the third gate structure further comprises a p-type work function layer disposed between the n-type work function layer and the barrier layer.